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MAX9271
16-Bit GMSL Serializer with Coax or
STP Cable Drive
33
Maxim Integrated
Cyclic Redundancy Check (CRC)
When CRC is enabled, the serializer adds 6 bits of CRC
to the input data. This reduces the available bits in the
input data word by 6, compared to the non-CRC case
(see
Table 2 for details). For example, 16 bits are avail-
able for input data instead of 22 bits when BWS = 0, and
24 bits instead of 30 bits when BWS = 1.
The CRC generator polynomial is x6 + x + 1 (as used in
the ITU-T G704 telecommunication standard).
The parity bit is still added when CRC is enabled,
because it is used for word-boundary detection. When
CRC is enabled, each data word is scrambled and then
the 6-bit CRC and 1-bit parity are added before the
8b/10b encoding.
At the deserializer, the CRC code is recalculated. If the
recalculated CRC code does not match the received
CRC code, an error is flagged. This CRC error is reported
to the error counter.
Hamming Code
Hamming code is a simple and effective error-correction
code to detect and/or correct errors. The MAX9271 seri-
alizer (when used with the MAX9272 GMSL deserializer)
uses a single-error correction, double-error detection per
pixel hamming-code scheme.
The serializer uses data interleaving for burst error toler-
ance. Burst errors up to 11 consecutive bits on the serial
link are corrected, and burst errors up to 31 consecutive
bits are detected.
Hamming code adds overhead similar to CRC. See
Table 2for details regarding the available input word size.
HS/VS Encoding and/or Tracking
HS/VS encoding by a GMSL serializer allows horizontal
and vertical synchronization signals to be transmitted
while conserving pixel data bandwidth. With HS/VS
encoding enabled, 10-bit pixel data with a clock up to
100MHz can be transmitted using one video pixel of
data per HS/VS transition, versus 8-bit data with a clock
up to 100MHz without HS/VS encoding. The deserializer
performs HS/VS decoding, tracks the period of the HS/
VS signals, and uses voting to filter HS/VS bit errors.
When using HS/VS encoding, use a minimum HS/VS low-
pulse duration of two PCLKIN cycles when DBL = 0 on
the MAX9271/MAX9273. When DBL = 1, use a minimum
low-pulse duration of five PCLKIN cycles and a minimum
high-pulse duration of two PCLKIN cycles. When using
hamming code with HS/VS encoding, do not send more
than two transitions every 16 PCLKIN cycles.
When the serializer uses double-input mode (DBL = 1)
the active duration, plus the blanking duration of HS or
VS signals, should be an even number of PCLKIN cycles.
If HS/VS tracking is used without HS/VS encoding, use
DIN0 for HSYNC and DIN1 for VSYNC. In this case, if
DBL values on the serializer and the deserializer are dif-
ferent, set the deserializer’s UNEQDBL register bit to 1.
If the serializer and deserializer have unequal DBL set-
tings and HVEN = 0, then HS/VS inversion should only
be used on the side that has DBL = 1. HS/VS encoding
sends packets when HSYNC or VSYNC is low, use H/V
inversion register bits if input HSYNC and VSYNC signals
use an active-low convention to send data packets dur-
ing the inactive pixel clock periods.
Serial Output
The driver output is programmable for two types of cable:
100I twisted pair and 50I coax (contact the factory for
serializers with 75I cable drive).
Table 8. Modulation Coefficients and
Maximum SDIV Settings
BWS
SPREAD-
SPECTRUM
SETTING (%)
MODULATION
COEFFICIENT
(dec)
SDIV UPPER
LIMIT (dec)
1
104
40
0.5
104
63
3
152
27
1.5
152
54
4
204
15
2
204
30
0
1
80
52
0.5
80
63
3
112
37
1.5
112
63
4
152
21
2
152
42