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參數(shù)資料
型號(hào): MAX9258AEVKIT#
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 25/53頁(yè)
文件大?。?/td> 0K
描述: EVAL KIT MAX9257A, MAX9258A
標(biāo)準(zhǔn)包裝: 1
系列: *
Maxim Integrated Products 31
MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
with UART/I2C Control Channel
ETO Timer
The ETO (end timeout) timer closes the control channel if
the ECU stops communicating for the ETO timeout period.
Configure register REG3[7:4] for both the MAX9257A and
the MAX9258A to select the divide ratio (ETODIV) for the
ETO clock as a function of the pixel clock (Table 25). The
timeout period is determined by counter bits REG3[3:0]
that increment once every ETO clock period. Write to
REG3[3:0] to determine the counter end time. The ETO
counter counts to the programmed ETOCNT + 1. Any
ECU activity resets the ETO timer. When the ECU stops
transmitting data for the ETO timeout period, the control
channel closes (Figure 23).
ETO
CLK
1
t
ETODIV (ETOCNT 1)
f
=
×
+
For example:
If the pixel clock frequency is set to 16MHz, ETODIV is
set to 1010 (ETODIV = 1024), and ETOCNT is set to 1001
(ETOCNT = 9), the ETO timer counts with the 15.625kHz
ETO clock (16MHz/1024) internally until it reaches 10 and
timer expires. The tETO is equal to tT x 1024 x 10 = 640Fs.
The default value for ETODIV is 1024 while the default
value for ETOCNT is 0. That means the ETO timeout
period is equal to 1,024 pixel clock cycles.
Table 25. ETO Clock Divide Ratio
Figure 22. Control Channel Closing Due to STO Timeout
REG3[7:4]
ETODIV
00XX
16
0100
16
0101
32
0110
64
0111
128
1000
256
1001
512
1010
1024
1011
2048
1100
4096
1101
8192
1110
16,384
1111
32,768
VIDEO
HSK
VSYNC_IN
SDI/O
CCEN
T1
T2
T3
TX
RX
DOUT_
FROZEN
T1 = TIME TO ENTER CONTROL CHANNEL
T2 = STO TIMEOUT PERIOD
T3 = CONTROL CHANNEL EXIT TIME DUE TO STO
HSK = HANDSHAKING BETWEEN THE MAX9257 AND THE MAX9258
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