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參數(shù)資料
型號: MAX9257AGTL/V+T
廠商: Maxim Integrated Products
文件頁數(shù): 28/53頁
文件大?。?/td> 0K
描述: IC SERDE PROG UART/I2C 40TQFN
標(biāo)準(zhǔn)包裝: 2,500
系列: *
Maxim Integrated Products 34
MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
with UART/I2C Control Channel
Powering the MAX9257A with Serialization Enabled
(REM = Ground at Power-Up)
When REM is grounded, the MAX9257A fully pow-
ers up when power is applied. The power-down bit
PD (REG4[4]) is disabled and serialization bit SEREN
(REG4[3]) is enabled. If PCLK_IN is not running, the
MAX9257A stays in the control channel. After PCLK_IN
is applied, the control channel times out due to STO,
ETO, or EF. The MAX9257A starts the handshaking after
the MAX9257A locks to PCLK after 32,768 clock cycles.
If PCLK_IN is running, serialization starts automatically
after PLL of the MAX9257A locks to PCLK_IN with default
values in the registers.
Remote Power-Up of the MAX9257A
(REM = Pulled Up to VCC)
When REM is pulled up to VCC, the MAX9257A wakes
up in a low power state, drawing less than 100FA supply
current. To wake-up the MAX9257A, the ECU first trans-
mits a dummy frame 0xDB and then waits at least 100Fs
to allow the MAX9257A’s internal analog circuitry to fully
power up. Then the ECU configures the MAX9257A reg-
isters, including a write to disable the PD bit (REG4[4])
so that the MAX9257A does not return back to the low
power state. Every packet needs to start with a synchro-
nization frame (see the UART section). If the PD bit is not
disabled within 70ms after transmitting the dummy frame,
the MAX9257A returns to the low power state and the
whole power-up sequence needs to be repeated. After
configuration is complete, the ECU also needs to enable
the SEREN bit to start the video phase.
At initial power-up with REM pulled to VCC, default value
of SEREN bit is 0, so STO and ETO timers are not active.
Control channel is enabled as long as SEREN is 0. This
allows the control channel to be used for extensive pro-
gramming at initial power-up without the channel timing
out. UART, parity, framing and packet errors in the con-
trol channel communications are reported if end frame is
used to close control channel (see the MAX9258A Error
Checking and Reporting section). For faster identification
of errors, verify every write command by reading back
the registers before enabling serialization.
Link Power-Down
When the control channel is open, the ECU writes to the
PD bit to power down the MAX9257A. In this case, to
power up the MAX9257A again, the power-up sequence
(REM = Pulled Up to VCC) section needs to be repeated.
The MAX9258A has a PD input that powers down the device.
MAX9258A Error Checking and Reporting
The MAX9258A has an open-drain ERROR output. This
output indicates various error conditions encountered
during the operation of the system. When an error con-
dition is detected and needs to be reported, ERROR
asserts low. ERROR indicates three error conditions:
UART, video parity, and PRBS errors.
UART Errors
During control channel communication in base mode, the
devices record UART frame, parity, and packet errors.
I2C errors are also recorded by MAX9257A when I2C
interface is enabled. If ECU closes the control channel
by using end frame (EF), the MAX9257A sends a special
internal UART frame back to the MAX9258A called error
frame. The MAX9257A UART and I2C errors are reset at
the next control channel. The MAX9258A receives the
error frame and records the error status in its UART error
register (REG13). ECU must use end frame to the close
control channel for the MAX9257A to report back UART
and I2C errors to the MAX9258A. Whenever one of the
bits in the UART error register is 1, ERROR asserts low.
The UART error register is reset when ECU reads it, and
ERROR deasserts high immediately if UART errors were
the only reason that ERROR was asserted low. If the
MAX9258A is not locked (LOCK = low), UART error is not
reported.
Video Parity Errors
When video parity check is enabled (REG0[3] in both
devices), the MAX9258A counts the number of video
parity errors by checking recovered video words. Value
of this counter is reflected in PAERRHI (8 MSB bits,
REG11) and PAERRLO (8 LSB bits, REG10). If the num-
ber of detected parity errors is greater than or equal
to the parity error threshold PATHRHI (REG9) and
PATHRLO (REG8), then ERROR asserts low. In this case,
ERROR deasserts high after next video phase starts if
video parity errors were the only reason that ERROR was
asserted low. To report parity errors in bypass mode,
program autoerror reset (AER) to 1 (REG1[5] = 1).
Autoerror Reset
The default method to reset errors is to read the respec-
tive error registers in the MAX9258A (registers 10, 11,
and 13). If errors were present before the next control
channel, the error count gets incremented to the previ-
ous number. By setting the autoerror reset (AER) bit to 1,
the error registers reset when the control channel ends.
Setting AER to 1 does not reset PRBS errors.
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