
M
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
8
_______________________________________________________________________________________
Test Circuits/Timing Diagrams (continued)
FREQUENCY
TIME
f
RxCLKOUT
(MAX)
f
RxCLKIN
f
RxCLKOUT
(MIN)
1 / f
SSM
Figure 10. Simplified Modulation Profile
RxCLKOUT
SSG
OPEN OR LESS THAN
±
10
μ
A LEAKAGE
2.5V
0.8V
RxCLKIN_
RxOUT_
RPLLS2
TIMING SHOWN FOR FALLING-EDGE STROBE (MAX9244/MAX9246/MAX9254)
PWRDWN = HIGH
Figure 9. Phase-Locked-Loop Set Time from SSG Change