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參數(shù)資料
| 型號： | MAX9226ETE+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 2/15頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DESERIALIZER LP 16-TQFN |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 功能： | 串行器/解串器 |
| 數(shù)據(jù)速率： | 200Mbps |
| 輸入類型： | 并聯(lián) |
| 輸出類型： | 并聯(lián) |
| 輸入數(shù)： | 1 |
| 輸出數(shù)： | 10 |
| 電源電壓： | 2.375 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 16-TQFN-EP（3x3） |
| 包裝： | 帶卷 (TR) |
MAX9225/MAX9226
Applications Information
PCLKIN Latch Edge
The parallel data input of the MAX9225 serializer is
latched on the rising edge of PCLKIN. Figure 3 shows
the serializer input timing.
PCLKOUT Strobe
The serial-data output of the MAX9226 deserializer is
valid on the rising edge of PCLKOUT. Figure 4 shows
the deserializer output timing.
Power-Down and Power-Up
Driving PWRDN low puts the MAX9225 in power-down
mode and sends a pulse to power down the MAX9226.
In power-down mode, the DLL is stopped, SDO+/SDO-
are high impedance to ground and differential, and the
LCDS link is weakly biased around (VDD - 0.8V). With
PWRDN and all inputs low, the combined MAX9225/
MAX9226 supply current is reduced to 3.5A or less.
Driving PWRDN high starts DLL lock to PCLKIN and ini-
tiates a MAX9226 power-up sequence. The MAX9225
LCDS output is not driven until the DLL locks. 11,264
clock cycles are required for the power-up and link syn-
chronization before valid DIN can be latched. See
Figure 6 for an overall power-up and power-down tim-
ing diagram. For normal operation, PCLKIN must be
running and settled before driving PWRDN high.
If VDD = 0, the LCDS outputs are high impedance to
ground and differential.
Ground-Shift Tolerance
The MAX9225/MAX9226 are designed to function nor-
mally in the event of a slight shift in ground potential.
However, the MAX9226 deserializer ground must be
within ±0.2V relative to the MAX9225 serializer ground
to maintain proper operation.
MAX9226 Output Buffer Supply (VDDO)
The MAX9226 parallel outputs are powered from VDDO,
which accepts a +1.71V to +3.465V supply, allowing
direct interface to inputs with 1.8V to 3.3V logic levels.
10-Bit, Low-Power, 10MHz-to-20MHz
Serializer and Deserializer Chipset
10
______________________________________________________________________________________
DIN[9:0]
PCLK IN
DIN
EXAMPLE
INPUT
PARALLEL DATA INPUT
LCDS SERIAL-DATA OUTPUT FOR EXAMPLE INPUT (SD0+/SDO-)
NOTE: OH1 AND OH2 ARE OPPOSITE POLARITY.
OH1
OH2
1
11
1
00
0
01
2
3
4
5
6
7
8
9
11
0
1
0
1
0
1
Figure 5. Multilevel LCDS Output Representation
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX9226EVKIT | 制造商:Maxim Integrated Products 功能描述:10-BIT LOW-POWER 10MHZ TO 20MHZ S - Rail/Tube |
| MAX922C/D | 功能描述:校驗(yàn)器 IC RoHS:否 制造商:STMicroelectronics 產(chǎn)品: 比較器類型: 通道數(shù)量: 輸出類型:Push-Pull 電源電壓-最大:5.5 V 電源電壓-最小:1.1 V 補(bǔ)償電壓（最大值）:6 mV 電源電流（最大值）:1350 nA 響應(yīng)時間: 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SC-70-5 封裝:Reel |
| MAX922CPA | 功能描述:校驗(yàn)器 IC Dual Comparator RoHS:否 制造商:STMicroelectronics 產(chǎn)品: 比較器類型: 通道數(shù)量: 輸出類型:Push-Pull 電源電壓-最大:5.5 V 電源電壓-最小:1.1 V 補(bǔ)償電壓（最大值）:6 mV 電源電流（最大值）:1350 nA 響應(yīng)時間: 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SC-70-5 封裝:Reel |
| MAX922CPA+ | 功能描述:校驗(yàn)器 IC Dual Comparator RoHS:否 制造商:STMicroelectronics 產(chǎn)品: 比較器類型: 通道數(shù)量: 輸出類型:Push-Pull 電源電壓-最大:5.5 V 電源電壓-最小:1.1 V 補(bǔ)償電壓（最大值）:6 mV 電源電流（最大值）:1350 nA 響應(yīng)時間: 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SC-70-5 封裝:Reel |
| MAX922CSA | 功能描述:校驗(yàn)器 IC Dual Comparator RoHS:否 制造商:STMicroelectronics 產(chǎn)品: 比較器類型: 通道數(shù)量: 輸出類型:Push-Pull 電源電壓-最大:5.5 V 電源電壓-最小:1.1 V 補(bǔ)償電壓（最大值）:6 mV 電源電流（最大值）:1350 nA 響應(yīng)時間: 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SC-70-5 封裝:Reel |
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