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參數(shù)資料
| 型號： | MAX9210EUM+TD |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 17/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DESERIALIZER PROG 48TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 功能： | 解串器 |
| 數(shù)據(jù)速率： | 1.785Gbps |
| 輸入類型： | LVDS |
| 輸出類型： | LVTTL，LVCMOS |
| 輸入數(shù)： | 3 |
| 輸出數(shù)： | 21 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TFSOP（0.240"，6.10mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 48-TSSOP |
| 包裝： | 帶卷 (TR) |
MAX9210/MAX9214/MAX9220/MAX9222
Programmable DC-Balance
21-Bit Deserializers
_______________________________________________________________________________________
9
To obtain DC balance on the data channels, the serial-
izer parallel data is inverted or not inverted, depending
on the sign of the digital sum at the word boundary.
Two complementary bits are appended to each group
of 7 parallel input data bits to indicate to the MAX9210/
MAX9214/MAX9220/MAX9222 deserializers whether
the data bits are inverted (see Figures 9 and 10). The
deserializer restores the original state of the parallel
data. The LVDS clock signal alternates duty cycles of
4/9 and 5/9, which maintain DC balance.
AC-Coupling Benefits
Bit errors experienced with DC-coupling can be elimi-
nated by increasing the receiver common-mode voltage
range by AC-coupling. AC-coupling increases the com-
mon-mode voltage range of an LVDS receiver to nearly
TxIN_ IS DATA FROM THE SERIALIZER.
TxIN1
TxIN7
TxIN8
TxIN14
TxIN15
+
-
CYCLE N + 1
CYCLE N
CYCLE N - 1
TxIN2
TxIN6
TxIN3
TxIN4
TxIN5
TxIN9
TxIN13
TxIN10
TxIN11
TxIN12
TxIN0
TxIN1
TxIN2
TxIN6
TxIN3
TxIN4
TxIN5
TxIN7
TxIN8
TxIN9
TxIN13
TxIN10
TxIN11
TxIN12
TxIN14
TxIN15
TxIN16
TxIN20
TxIN17
TxIN18
TxIN19
TxIN0
TxIN1
TxIN7
TxIN8
TxIN14
TxIN15
TxIN16
TxIN20
TxIN17
TxIN18
TxIN19
TxIN0
RxCLK IN
RxIN1
RxIN0
RxIN2
Figure 9. Deserializer Serial Input in Non-DC-Balanced Mode
TxIN_, DCA_, AND DCB_ ARE DATA FROM THE SERIALIZER.
DCA0
DCB1
DCA1
DCB2
DCA2
CYCLE N + 1
CYCLE N
CYCLE N - 1
TxIN2
TxIN6
TxIN3
TxIN4
TxIN5
TxIN9
TxIN13
TxIN10
TxIN11
TxIN12
TxIN2
TxIN3
TxIN4
DCA0
TxIN5
TxIN6
DCB0
TxIN9
TxIN10
TxIN11
DCA1
TxIN12
TxIN13
DCB1
TxIN16
TxIN17
TxIN18
DCA2
TxIN19
TxIN20
DCB2
TxIN0
TxIN1
TxIN7
TxIN8
TxIN14
TxIN15
TxIN16
TxIN20
TxIN17
TxIN18
TxIN19
DCB0
RxCLK IN
RxIN1
RxIN0
RxIN2
TxIN1
TxIN8
TxIN15
TxIN0
TxIN7
TxIN14
+
-
Figure 10. Deserializer Serial Input in DC-Balanced Mode
0.8V
PWRDWN
RxCLK IN
RxOUT_
RxCLK OUT
RPDD
HIGH-Z
Figure 8. Power-Down Delay
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX9211ETM | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Programmable DC-Balanced 21-Bit Serializers |
| MAX9211EUM | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Programmable DC-Balanced 21-Bit Serializers |
| MAX9212 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Programmable DC-Balance 21-Bit Deserializers |
| MAX9212ETM | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Programmable DC-Balance 21-Bit Deserializers |
| MAX9212EUM | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Programmable DC-Balance 21-Bit Deserializers |
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