參數(shù)資料
型號(hào)： MAX9206EAI+
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 8/12頁(yè)
文件大?。?/td> 0K
描述： IC DESERIALIZER LVDS 28-SSOP
其它有關(guān)文件： Automotive Product Guide
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 46
功能： 解串器
數(shù)據(jù)速率： 660Mbps
輸入類型： LVDS
輸出類型： LVTTL，LVCMOS
輸入數(shù)： 1
輸出數(shù)： 10
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 28-SSOP（0.209"，5.30mm 寬）
供應(yīng)商設(shè)備封裝： 28-SSOP
包裝： 管件
產(chǎn)品目錄頁(yè)面： 1424 (CN2011-ZH PDF)
MAX9206/MAX9208
10-Bit Bus LVDS Deserializers
Pin Description
PIN
NAME
FUNCTION
1, 12, 13
AGND
Analog Ground
2
RCLK_R/
F
Recovered Clock Strobe Edge Select. LVTTL/LVCMOS level input. Drive RCLK_ R/
F high to strobe
ROUT_ on the rising edge of RCLK. Drive RCLK_R/
F low to strobe ROUT_ on the falling edge of
RCLK.
3
REFCLK
PLL Reference Clock. LVTTL/LVCMOS level input.
4, 11
AVCC
Analog Power Supply. Bypass AVCC with a 0.1μF and a 0.001μF capacitor to AGND.
5
RI+
Serial Data Input. Noninverting BLVDS differential input.
6
RI-
Serial Data Input. Inverting BLVDS differential input.
7
PWRDN
Power Down. LVTTL/LVCMOS level input. Drive
PWRDN low to stop the PLL and put ROUT_, LOCK,
and RCLK in high impedance.
8
REN
Output Enable. LVTTL/LVCMOS level input. Drive REN low to put ROUT_ and RCLK in high
impedance.
LOCK remains active, indicating the status of the serial input.
9
RCLK
Recovered Clock. LVTTL/LVCMOS level output. Use RCLK to strobe ROUT_.
10
LOCK
Lock Indicator. LVTTL/LVCMOS level output.
LOCK goes low when the PLL has achieved frequency
and phase lock to the serial input, and the framing bits have been identified.
14, 20,
22
DGND
Digital Ground
15–19,
24–28
ROUT9–
ROUT0
Parallel Output Data. LVTTL/LVCMOS level outputs. ROUT_ is valid on the second selected strobe
edge of RCLK after
LOCK goes low.
21, 23
DVCC
Digital Power Supply. Bypass DVCC with a 0.1μF and a 0.001μF capacitor to DGND.
Figure 1. Worst-Case ICC Test Pattern
0
END
BIT
9
8
7
6
5
4
3
1
0
START
BIT
END
BIT
9
7
6
5
4
3
2
1
2
1
82
START
BIT
TDD
RCLK_R/F = HIGH
START
BIT
RI
RCLK
ODD
ROUT
EVEN
ROUT
Test Circuits/Timing Diagrams
_______________________________________________________________________________________
5
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MAX9206EAI/V+ 功能描述:串行器/解串器 - Serdes 10-Bit Bus LVDS Serializer RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64
MAX9206EAI/V+T 功能描述:串行器/解串器 - Serdes 10-Bit Bus LVDS Serializer RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64
MAX9206EAI+ 功能描述:串行器/解串器 - Serdes 10-Bit Bus LVDS Serializer RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64
MAX9206EAI+C9F 制造商:Maxim Integrated Products 功能描述:10-BIT BUS LVDS SERIALIZERS. - Rail/Tube
MAX9206EAI+T 功能描述:串行器/解串器 - Serdes 10-Bit Bus LVDS Serializer RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64
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