參數(shù)資料
型號: MAX9203ESA+T
廠商: Maxim Integrated Products
文件頁數(shù): 7/8頁
文件大小: 0K
描述: IC COMPARATOR LP 8-SOIC
其它有關(guān)文件: Automotive Product Guide
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
類型: 帶鎖銷
元件數(shù): 1
輸出類型: TTL
電壓 - 電源,單路/雙路(±): 4.75 V ~ 10.5 V,±2.375 V ~ 5.75 V
電壓 - 輸入偏移(最小值): 4mV @ ±5V
電流 - 輸入偏壓(最小值): 5µA @ ±5V
電流 - 靜態(tài)(最大值): 2mA,1.6mA,800µA
CMRR, PSRR(標(biāo)準(zhǔn)): 86.02dB CMRR,86.02dB PSRR
工作溫度: -40°C ~ 85°C
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
安裝類型: 表面貼裝
包裝: 帶卷 (TR)
_______________________________________________________________________________________
7
MAX9201/9202/9203
Low Cost, 7ns, Low-Power
Voltage Comparators
Power Supplies
The MAX9201/MAX9202/MAX9203 can be powered
from separate analog and digital supplies or from a sin-
gle +5V supply. The analog supply can range from +5V
to +10V with VEE grounded for single-supply operation
(Figures 1a and 1b) or from a split ±5V supply (Figure
1c). The VDD digital supply always requires +5V.
In high-speed, mixed-signal applications where a com-
mon ground is shared, a noisy digital environment can
adversely affect the analog input signal. When set up with
separate supplies, the MAX9201/MAX9202/MAX9203
isolate analog and digital signals by providing a separate
analog ground (VEE) and digital ground (GND).
Definition of Terms
VOS
Input Offset Voltage: Voltage applied be-
tween the two input terminals to obtain TTL
logic threshold (+1.4V) at the output.
VIN
Input Voltage Pulse Amplitude: Usually set
to 100mV for comparator specifications.
VOD
Input Voltage Overdrive: Usually set to 5mV
and in opposite polarity to VIN for comparator
specifications.
tpd+
Input to Output High Delay: The propagation
delay measured from the time the input signal
crosses the input offset voltage to the TTL
logic threshold (+1.4V) of an output low to high
transition.
tpd-
Input to Output Low Delay: The propagation
delay measured from the time the input signal
crosses the input offset voltage to the TTL
logic threshold (+1.4V) of an output high to low
transition.
tpd+ (D) Latch Disable to Output High Delay: The
propagation delay measured from the latch
signal crossing the TTL logic threshold
(+1.4V) in a low to high transition to the point
of the output crossing TTL threshold (+1.4V)
in a low to high transition.
tpd- (D) Latch Disable to Output Low Delay: The
propagation delay measured from the latch
signal crossing the TTL threshold (+1.4V) in a
low to high transition to the point of the output
crossing TTL threshold (+1.4V) in a high to
low transition.
ts
Minimum Setup Time: The minimum time,
before the negative transition of the latch sig-
nal, that an input signal change must be pre-
sent in order to be acquired and held at the
outputs.
th
Minimum Hold Time: The minimum time,
after the negative transition of the latch sig-
nal, that an input signal must remain
unchanged in order to be acquired and held
at the output.
tpw (D)
Minimum Latch Disable Pulse Width: The
minimum time that the latch signal must
remain high in order to acquire and hold an
input signal change.
Figure 2. MAX9201/MAX9202/MAX9203 Diagram
Figure 3. tPD+ Response Time to 5mV Overdrive
LATCH
ENABLE
INPUT
tpd
tpd+ (D)
tpw (D)
ts
th
VIN
VOD
VOS
LATCH
COMPARE
LATCH
COMPARE
COMPARATOR
OUTPUT
1.4V
5ns/div
OUTPUT
INPUT
VOD + 5mV
50mV/div
1V/div
0V
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