
M
Quad LVDS Receiver with Hysteresis
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9
Cables and Connectors
Interconnect for LVDS typically has a controlled differ-
ential impedance of 100
. Use cables and connectors
that have matched differential impedance to minimize
impedance discontinuities. Avoid the use of unbal-
anced cables such as ribbon or simple coaxial cable.
Balanced cables such as twisted pair offer superior
signal quality and tend to generate less EMI due to
magnetic field canceling effects. Balanced cables pick
up noise as common mode, which is rejected by the
LVDS receiver.
Termination
The MAX9179 requires external termination resistors.
The input termination resistor used on each active
channel should match the differential impedance of the
transmission line. Place the termination resistor as
close to the MAX9179 receiver input as possible. Use
1% surface-mount resistors.
Board Layout
Keep the LVDS input and LVCMOS output signals sepa-
rated from each other to reduce crosstalk; 180 degrees of
separation between LVDS inputs and LVCMOS outputs is
recommended. Because there are leads on all sides, this
separation requires special attention when laying out
traces for the QFN package.
A four-layer printed circuit board with separate layers
for power, ground, LVDS inputs, and single-ended
logic signals is recommended. Separate the LVDS sig-
nals from the single-ended signals with power and
ground planes for best results.
IEC 61000-4-2 Level 4 ESD Protection
The IEC 61000-4-2 standard (Figure 7) specifies ESD
tolerance for electronic systems. The IEC61000-4-2
model specifies a 150pF capacitor that is discharged
into the device through a 330
resistor. The MAX9179
LVDS inputs are rated for IEC61000-4-2 level 4 (±8kV
Contact Discharge and ±15kV Air-Gap Discharge). The
Human Body Model (HBM) (Figure 8) specifies a 100pF
capacitor that is discharged into the device through a
1.5k
resistor. The IEC 61000-4-2 discharges higher
peak current and more energy than the HBM due to the
lower series resistance and larger capacitor.
Chip Information
TRANSISTOR COUNT: 1173
PROCESS: CMOS
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
Cs
100pF
R
C
1M
R
D
1.5k
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
Figure 8. Human Body Test Model
IN1+
IN1-
IN2+
IN2-
IN3+
IN3-
IN4+
IN4-
EN
EN
OUT1
OUT2
OUT3
OUT4
Functional Diagram
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
Cs
150pF
R
50
TO 100
R
D
330
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
Figure 7. IEC61000-4-2 Test Model