參數(shù)資料
型號: MAX9130EXT+T
廠商: Maxim Integrated Products
文件頁數(shù): 7/8頁
文件大?。?/td> 0K
描述: IC RCVR SNGL LVDS SC70-6
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,500
類型: 接收器
驅(qū)動器/接收器數(shù): 0/1
規(guī)程: LVDS
電源電壓: 3 V ~ 3.6 V
安裝類型: 表面貼裝
封裝/外殼: 6-TSSOP,SC-88,SOT-363
供應(yīng)商設(shè)備封裝: SC-70-6
包裝: 帶卷 (TR)
Differential Traces
Input trace characteristics affect the performance of the
MAX9130. Use controlled-impedance PC board traces,
typically 100
. Match the termination resistor to this
characteristic impedance.
Eliminate reflections and ensure that noise couples as
common mode by running the differential traces close
together. Reduce skew by matching the electrical
length of the traces. Excessive skew can result in a
degradation of magnetic field cancellation.
Input differential signals should be routed close to each
other to cancel their external magnetic field. Maintain a
constant distance between the differential traces to
avoid discontinuities in differential impedance. Minimize
the number of vias to further prevent impedance dis-
continuities.
Cables and Connectors
Transmission media should typically have a controlled
differential impedance of 100
. Use cables and con-
nectors that have matched differential impedance to
minimize impedance discontinuities.
Avoid the use of unbalanced cables such as ribbon or
simple coaxial cable. Balanced cables such as twisted
pair offer superior signal quality and tend to generate
less EMI due to canceling effects. Balanced cables
tend to pick up noise as common mode, which is
rejected by the LVDS receiver.
Termination
The MAX9130 requires an external termination resistor.
The termination resistor should match the differential
impedance of the transmission line. Termination resis-
tance is typically 100
but may range between 90 to
132
, depending on the characteristic impedance of
the transmission medium.
When using the MAX9130, minimize the distance
between the input termination resistor and the MAX9130
receiver inputs. Use 1% surface-mount resistors.
Board Layout
For LVDS applications, use a four-layer PC board that
provides separate layers for power, ground, and
input/output signals is recommended. Keep the LVDS
input signals away from the output LVCMOS/LVTTL sig-
nal to prevent coupling (Figure 4). To minimize
crosstalk, do not run the output in parallel with the
inputs.
Chip Information
TRANSISTOR COUNT: 201
PROCESS: CMOS
MAX9130
Single 500Mbps LVDS Line Receiver in SC70
_______________________________________________________________________________________
7
20%
50%
80%
COMMON-MODE VOLTAGE: VCM = (VIN+ + VIN-) / 2
DIFFERENTIAL INPUT VOLTAGE: VID = (VIN+) - (VIN-)
80%
VOH
VOL
tTLH
tTHL
VOUT
VID = 0
VID
VIN-
VIN+
tPLHD
tPHLD
Figure 3. Propagation Delay and Transition Time Waveforms
U1
R1
U1: MAX9130
R1, C1 ARE 0402 TYPE
IN-
(LVDS
INPUTS)
OUT
IN+
GND
(LVTTL/LVCMOS OUTPUT)
C1
0.01
F
VCC
Figure 4. Board Layout
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