參數(shù)資料
型號(hào): MAX9124ESE+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 3/9頁(yè)
文件大?。?/td> 0K
描述: IC DRVR QUAD LVDS 16-SOIC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
類型: 驅(qū)動(dòng)器
驅(qū)動(dòng)器/接收器數(shù): 4/0
規(guī)程: LVDS
電源電壓: 3 V ~ 3.6 V
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-SOIC
包裝: 帶卷 (TR)
MAX9124
Quad LVDS Line Driver
_______________________________________________________________________________________
3
SWITCHING CHARACTERISTICS
(VCC = +3.0V to +3.6V, RL = 100
±1%, CL = 10pF, TA = -40°C to +85°C. Typical values are at VCC = +3.3V, TA = +25°C, unless
otherwise noted.) (Notes 4, 5, 6)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Differential Propagation Delay
High to Low
tPHLD
Figures 2 and 3
0.8
1.42
2.0
ns
Differential Propagation Delay
Low to High
tPLHD
Figures 2 and 3
0.8
1.44
2.0
ns
Differential Pulse Skew (Note 7)
tSKD1
Figures 2 and 3
0.02
0.25
ns
Differential Channel-to-Channel
Skew (Note 8)
tSKD2
Figures 2 and 3
0.35
ns
Differential Part-to-Part Skew
(Note 9)
tSKD3
Figures 2 and 3
0.8
ns
Differential Part-to-Part Skew
(Note 10)
tSKD4
Figures 2 and 3
1.2
ns
Rise Time
tTLH
Figures 2 and 3
0.1
0.35
0.7
ns
Fall Time
tTHL
Figures 2 and 3
0.1
0.35
0.7
ns
Disable Time High to Z
tPHZ
Figures 4 and 5
5
ns
Disable Time Low to Z
tPLZ
Figures 4 and 5
5
ns
Enable Time Z to High
tPZH
Figures 4 and 5
5
ns
Enable Time Z to Low
tPZL
Figures 4 and 5
5
ns
Maximum Operating Frequency
(Note 11)
fMAX
400
MHz
Note 1: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are 100% tested
at TA = +25°C.
Note 2: Currents into the device are positive, and current out of the device is negative. All voltages are referenced to ground except
VOD.
Note 3: Guaranteed by correlation data.
Note 4: AC parameters are guaranteed by design and characterization.
Note 5: CL includes probe and jig capacitance.
Note 6: Signal generator conditions for dynamic tests: VOL = 0, VOH = 3V, f = 100MHz, 50% duty cycle, RO = 50
, tR ≤ 1ns, tF
1ns (0% to 100%).
Note 7: tSKD1 is the magnitude difference of differential propagation delay. tSKD1 = |tPHLD - tPLHD|.
Note 8: tSKD2 is the magnitude difference of tPHLD or tPLHD of one channel to the tPHLD or tPLHD of another channel on the same
device.
Note 9: tSKD3 is the magnitude difference of any differential propagation delays between devices at the same VCC and within 5°C
of each other.
Note 10: tSKD4 is the magnitude difference of any differential propagation delays between devices operating over the rated supply
and temperature ranges.
Note 11: fMAX signal generator conditions: VOL = 0, VOH = 3V, f = 400MHz, 50% duty cycle, RO = 50
, tR ≤ 1ns, tF ≤ 1ns (0% to
100%). Transmitter output criteria: duty cycle = 45% to 55%, VOD
≥ 250mV.
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