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參數(shù)資料
| 型號： | MAX9109EXT+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 7/13頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC COMPAR LP SGL SC70-6 |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 帶鎖銷 |
| 元件數(shù)： | 1 |
| 輸出類型： | TTL |
| 電壓 - 電源，單路/雙路(±)： | 4.5 V ~ 5.5 V |
| 電壓 - 輸入偏移（最小值）： | 1.6mV @ 5V |
| 電流 - 輸入偏壓（最小值）： | 0.125µA @ 5V |
| 電流 - 靜態(tài)（最大值）： | 700µA |
| CMRR, PSRR（標(biāo)準(zhǔn)）： | 86.02dB CMRR，86.02dB PSRR |
| 傳輸延遲（最大）： | 25ns |
| 磁滯： | 2mV |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 6-TSSOP，SC-88，SOT-363 |
| 安裝類型： | 表面貼裝 |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁面： | 1391 (CN2011-ZH PDF) |
| 其它名稱： | MAX9109EXT+TDKR |
MAX9107/MAX9108/MAX9109
25ns, Dual/Quad/Single, Low-Power,
TTL Comparators
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +5V, VCM = 0, VLE = 0 (MAX9109 only), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
Latch Hold Time
Latch Setup Time
Latch Input Current
Latch Input Voltage Low
Latch Input Voltage High
Propagation Delay Skew
Differential Propagation Delay
Propagation Delay
PARAMETER
SYMBOL
tPD+, tPD-
tPD
tPDskew
VIH
VIL
IIH, IIL
ts
th
(Note 8)
VIN = 100mV, VOD = 10mV
(Note 7)
VIN = 100mV, VOD = 10mV
(Note 6)
VIN = 100mV, VOD = 10mV
CONDITIONS
MIN
TYP
MAX
25
1
5
2.0
0.8
0.4
1
2
ns
A
V
ns
UNITS
Note 1:
Devices are 100% production tested at TA = +25°C. All temperature limits are guaranteed by design.
Note 2:
Input Offset Voltage is defined as the center of the input-referred hysteresis zone. Specified for VCM = 0. See Figure 1.
Note 3:
Trip Point is defined as the input voltage required to make the comparator output change state. The difference
between upper (VTRIP+) and lower (VTRIP-) trip points is equal to the width of the input-referred hysteresis zone (VHYST).
Specified for an input common-mode voltage (VCM) of 0. See Figure 1.
Note 4:
Inferred from the CMRR test. Note that a correct logic result is obtained at the output, provided that at least one input is
within the VCMR limits. Note also that either or both inputs can be driven to the upper or lower absolute maximum limit with-
out damage to the part.
Note 5:
Tested over the full-input voltage range (VCMR).
Note 6:
Differential Propagation Delay is specified as the difference between any two channels in the MAX9107/MAX9108 (both
outputs making either a low-to-high or a high-to-low transition).
Note 7:
Propagation Delay Skew is specified as the difference between any single channel’s output low-to-high transition (tPD+)
and high-to-low transition (tPD-).
Note 8:
Latch specifications apply to MAX9109 only. See Figure 2.
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