M
PWRON
Drive PWRON low or leave PWRON open to place the
MAX8621Y/MAX8621Z in power-down mode and
reduce supply current to 5μA (typ). In power-down, the
control circuitry, internal-switching p-channel MOSFET,
and the internal synchronous rectifier (n-channel
MOSFET) turn off (BUCK1 and BUCK2), and LX_
becomes high impedance. In addition, all four LDOs
are disabled. Connect PWRON to IN or logic-high to
enable the MAX8621Y/MAX8621Z.
EN2
enables and
disables OUT2 when PWRON is high.
OUT2 Enable (
EN2
)
Drive
EN2
high to disable OUT2. Drive
EN2
low or
leave open to enable OUT2.
EN2
is internally pulled to
GND by an 800k
Ω
(typ) pulldown resistor. If the
MAX8621Y/MAX8621Z are powered down using
PWRON (PWRON = low), OUT2 does not power
regardless of the status of
EN2
.
Reset Output (
RESET
)
The reset circuit is active both at power-up and power-
down.
RESET
asserts low when V
OUT1
drops below
87% (typ) of regulation.
RESET
deasserts 60ms after
V
OUT1
rises above 87% (typ) of regulation.
RESET
is
pulled up through an internal 14k
Ω
resistor to OUT1.
Undervoltage Lockout
Initial power-up of the MAX8621Y/MAX8621Z occurs
when V
IN
is greater than 2.85V (typ) and PWRON
asserts. Once V
IN
exceeds 2.85V (typ), the undervolt-
age lockout has 0.5V of hysteresis, allowing the V
IN
operating range to drop down to 2.35V (typ) without
shutting down.
Current Limiting
The MAX8621Y/MAX8621Z OUT1 and OUT2 LDOs limit
their output current to 550mA (typ). OUT3 and OUT4
LDOs limit their output current to 360mA (typ). If the LDO
output current exceeds the current limit, the correspond-
ing LDO output voltage drops. The step-down converters
(BUCK1 and BUCK2) limit the p-channel MOSFET to
670mA (min) and the n-channel MOSFET to 750mA (min).
Reference Bypass Capacitor
Node (REFBP)
An external 0.01μF bypass capacitor and an internal
100k
Ω
(typ) resistor at REFBP create a lowpass filter for
LDO noise reduction. OUT1, OUT2, OUT3, and OUT4
exhibit 45μV
RMS
of output voltage noise with C
REFBP
=
0.01μF, C
OUT1
= C
OUT2
= 4.7μF, and C
OUT3
= C
OUT4
= 2.2μF.
Thermal-Overload Protection
Thermal-overload protection limits total power dissipa-
tion in the MAX8621Y/MAX8621Z. Independent thermal-
protection circuits monitor the step-down converters
and the linear-regulator circuits. When the junction tem-
perature exceeds T
J
= +160°C, the thermal-overload
protection circuit disables the corresponding circuitry,
allowing the IC to cool. The LDO thermal-overload pro-
tection circuit enables the LDOs after the LDO junction
temperature cools down, resulting in pulsed LDO out-
puts during continuous thermal-overload conditions. The
step-down converter’s thermal-overload protection
circuitry enables the step-down converter after the
junction temperature cools down. Thermal-overload
protection safeguards the MAX8621Y/MAX8621Z in the
event of fault conditions. For continuous operation, do
not exceed the absolute maximum junction-temperature
rating of T
J
= +150°C.
Applications Information
Step-Down DC-DC Converter
Setting the Step-Down Output Voltage
Select an output voltage for BUCK1 between 0.6V and
3.3V by connecting FB1 to a resistive voltage-divider
between LX1 and GND. Choose R2 (Figure 3) for a rea-
sonable bias current in the resistive divider. A wide range
of resistor values is acceptable, but a good starting point
is to choose R2 as 100k
Ω
. Then, R1 (Figure 3) is given by:
where V
FB
= 0.6V. For BUCK2, R3 and R4 are calculated
using the same methods.
Input Capacitor
The input capacitor, C
IN1
, reduces the current peaks
drawn from the battery or input power source and
reduces switching noise in the IC. The impedance of
C
IN1
at the switching frequency should be kept very
low. Ceramic capacitors with X5R or X7R dielectrics are
highly recommended due to their small size, low ESR,
and small temperature coefficients. Due to the
MAX8621Y/MAX8621Z step-down converter’s fast soft-
start, the input capacitance can be very low. Use a
10μF ceramic capacitor or an equivalent amount of
multiple capacitors in parallel between IN1 and ground.
Connect C
IN1
as close to the IC as possible to minimize
the impact of PC board trace inductance. Use a 4.7μF
ceramic capacitor from IN2 to ground and a second
4.7μF ceramic capacitor from IN3 to ground.
R
R
V
V
OUT
FB
1
2
1
=
Dual Step-Down DC-DC Power-Management ICs
for Portable Devices
12
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