參數(shù)資料
型號(hào): MAX8588
廠商: Maxim Integrated Products, Inc.
英文描述: 8-Line To 1-Line Data Selectors/Multiplexers 20-LCCC -55 to 125
中文描述: 高效率、低IQ PMIC,帶有動(dòng)態(tài)內(nèi)核,用于PDA和智能電話
文件頁(yè)數(shù): 8/31頁(yè)
文件大?。?/td> 572K
代理商: MAX8588
M
High-Efficiency, Low-I
Q
PMIC with
Dynamic Core for PDAs and Smartphones
8
_______________________________________________________________________________________
PARAMETER
CONDITIONS
MIN
2.993
1.208
2.25
62
-50
MAX
3.307
1.256
2.60
69
UNITS
DBI = IN (for preset)
With resistors at LBI
DBI Threshold (Falling)
Hysteresis is 5% (typ)
V
RSO
Threshold (Falling)
RSO
Deassert Delay
LBI Input Bias Current
DBI Input Bias Current
LOGIC INPUTS AND OUTPUTS
Voltage on REG7, hysteresis is 5% (typ)
V
ms
nA
nA
75
LBO
,
DBO
, POK,
RSO
, SDA Output
Low Level
2.6V
V7
5.5V, sinking 1mA
0.4
V
LBO
,
DBO
, POK,
RSO
, SDA Output
Low Level
V7
= 1V, sinking 100μA
0.4
V
LBO
,
DBO
, POK,
RSO
Output-High
Leakage Current
Pin
= 5.5V
0.2
μA
ON_, SCL, SDA,
SLP
, PWM3,
MR
,
SRAD Input High Level
2.6V
V
IN
5.5V
1.6
V
ON_, SCL, SDA,
SLP
, PWM3,
MR
,
SRAD Input Low Level
2.6V
V
IN
5.5V
0.4
V
ON_, SCL, SDA,
SLP
, PWM3,
MR
,
SRAD Input Leakage Current
Pin = GND, 5.5V
-1
+1
μA
SERIAL INTERFACE
Clock Frequency
400
kHz
Bus Free Time Between START and
STOP
1.3
μs
Hold Time Repeated START
Condition
0.6
μs
CLK Low Period
CLK High Period
1.3
0.6
μs
μs
Setup Time Repeated START
Condition
0.6
μs
DATA Hold Time
DATA Setup Time
Setup Time for STOP Condition
0
μs
ns
μs
100
0.6
ELECTRICAL CHARACTERISTICS (continued)
(V
IN
= 3.6V, V
BKBT
= 3.0V, V
LBI
= 1.1V, V
DBI
= 1.35V, circuit of Figure 5,
T
A
= -40°C to +85°C
, unless otherwise noted.) (Note 5)
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