參數(shù)資料
型號: MAX8545EUB
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 穩(wěn)壓器
英文描述: Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset 16-CFP -55 to 125
中文描述: SWITCHING CONTROLLER, 360 kHz SWITCHING FREQ-MAX, PDSO10
封裝: MO-187CBA, MICRO, SOP-10
文件頁數(shù): 12/18頁
文件大?。?/td> 343K
代理商: MAX8545EUB
M
Low-Cost, Wide Input Range, Step-Down
Controllers with Foldback Current Limit
12
______________________________________________________________________________________
with DH and DL to slow down the switching transitions.
However, adding series resistors increases the power
dissipation of the MOSFET, so ensure temperature rat-
ings of the MOSFET are not exceeded.
Input-Capacitor Selection
The input capacitors (C2 and C3 in Figure 1) reduce
noise injection and current peaks drawn from the input
supply. The input capacitor must meet the ripple-cur-
rent requirement (I
RMS
) imposed by the switching cur-
rents. The RMS input ripple current is given by:
For optimal circuit reliability, choose a capacitor that
has less than 10
°
C temperature rise at the RMS current.
I
RMS
is maximum when the input voltage equals 2 x
V
OUT
, where I
RMS
= 1/2 I
LOAD
.
Output Capacitor Selection
The key parameters for the output capacitor are the
actual capacitance value, the equivalent series resis-
tance (ESR), the equivalent series inductance (ESL),
and the voltage-rating requirements. All these parame-
ters affect the overall stability, output ripple voltage,
and transient response.
The output ripple has three components: variations in the
charge stored in the output capacitor, the voltage drop
across the ESR, and the voltage drop across the ESL.
V
RIPPLE
= V
RIPPLE(ESR)
+ V
RIPPLE(C)
+ V
RIPPLE(ESL)
The output voltage ripple as a consequence of the ESR
and output capacitance is:
where I
P-P
is the peak-to-peak inductor current (see the
Inductor Selection
section).
While these equations are suitable for initial capacitor
selection to meet the ripple requirement, final values
may also depend on the relationship between the LC
double-pole frequency and the capacitor ESR-zero fre-
quency. Generally, the ESR zero is higher than the LC
double pole; however, it is preferable to keep the ESR
zero close to the LC double pole when possible to
negate the sharp phase shift of the typically high-Q
double LC pole (see the
Compensation Design
sec-
tion). Aluminum electrolytic or POS capacitors are rec-
ommended. Higher output current requires multiple
capacitors to meet the output ripple voltage.
The MAX8545/MAX8546/MAX8548s
response to a load
transient depends on the selected output capacitor. After
a load transient, the output instantly changes by (ESR x
I
LOAD
) + (ESL x dI/dt). Before the controller can
respond, the output deviates further depending on the
inductor and output capacitor values. After a short period
of time (see the
Typical Operating Characteristics
), the
controller responds by regulating the output voltage back
to its nominal state. The controller response time
depends on the closed-loop bandwidth. Higher band-
width results in faster response time, preventing the out-
put voltage from further deviation.
Do not exceed the
capacitor’s voltage or ripple-current ratings
.
Boost Diode and Capacitor Selection
A low-current Schottky diode, such as the CMPSH-3
from Central Semiconductor, works well for most appli-
cations. Do not use large power diodes since higher
junction capacitance can charge up BST to LX voltage
that could exceed the device rating of 6V. The boost
capacitor should be in the range of 0.1μF to 0.47μF,
depending on the specific input and output voltages
and the external components and PC board layout. The
boost capacitance needs to be as large as possible to
prevent it from charging to excessive voltage, but small
enough to adequately charge during the minimum low-
side MOSFET conduction time, which happens at the
maximum operating duty cycle (this occurs at the mini-
mum input voltage). In addition, ensure the boost
capacitor does not discharge to below the minimum
gate-to-source voltage required to keep the high-side
MOSFET fully enhanced for lowest on-resistance. This
minimum gate-to-source voltage V
GS(MIN)
is deter-
mined by:
where Qg is the total gate charge of the high-side
MOSFET and C
BOOST
is the boost capacitor value.
Compensation Design
The MAX8545/MAX8546/MAX8548 use a voltage-mode
control scheme that regulates the output voltage. This is
done by comparing the error amplifier
s output (COMP) to
a fixed internal ramp. The inductor and output capacitor
create a double pole at the resonant frequency, which
V
V
Q
C
GS MIN
(
L
G
BOOST
)
=
V
I
ESR
V
I
C
f
V
V
ESL
L ESL
I
V
V
f
L
V
V
RIPPLE ESR
P P
RIPPL( )
P P
OUT
IN
×
SW
RIPPLE ESL
P P
IN
OUT
×
SW
OUT
IN
(
)
(
)
=
×
=
×
×
=
=
8
I
I
V
V
V
V
RMS
LOAD
OUT
IN
OUT
IN
=
×
×
(
)
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