參數(shù)資料
型號(hào): MAX8523
廠商: Maxim Integrated Products, Inc.
英文描述: High-Speed. Dual-Phase Gate Driver for Multiphase. Step-Down Converters
中文描述: 高速、雙相柵極驅(qū)動(dòng)器,用于多相、降壓型轉(zhuǎn)換器
文件頁數(shù): 9/14頁
文件大?。?/td> 296K
代理商: MAX8523
M
PWM Buc k Converters with Bypass FET
for N-CDMA/W-CDMA Handsets
_______________________________________________________________________________________
9
rent to the output filter capacitor and load until the induc-
tor current reaches the skip peak current limit. Then the
main switch turns off, and the magnetic field in the induc-
tor collapses, while current flows through the synchro-
nous rectifier to the output filter capacitor and the load.
The synchronous rectifier is turned off when the inductor
current reaches zero. The MAX8500
MAX8504 wait until
the skip comparator senses a low output voltage again.
Forc ed-PWM Operation
Connect
SKIP
to BATT for forced-PWM operation.
Forced-PWM operation is desirable in sensitive RF and
data-acquisition applications to ensure that switching
harmonics do not interfere with sensitive IF and data-
sampling frequencies. A minimum load is not required
during forced-PWM operation since the synchronous
rectifier passes reverse-inductor current as needed to
allow constant-frequency operation with no load. Forced-
PWM operation uses higher supply current with no load
(3.3mA typ) compared to skip mode (280μA typ).
100% Duty-Cyc le Operation and Dropout
The maximum on-time can exceed one internal oscilla-
tor cycle, which permits operation at 100% duty cycle.
Near dropout, cycles may be skipped, reducing switch-
ing frequency. However, voltage ripple remains small
because the current ripple is still low. As the input volt-
age drops even further, the duty cycle increases until
the internal P-channel MOSFET stays on continuously.
Dropout voltage at 100% duty cycle is the output cur-
rent multiplied by the sum of the internal PMOS on-resis-
tance (0.35
typ) and the inductor resistance. Once the
output voltage drops by 5%, the PFET bypass LDO
(MAX8500
MAX8503) turns on and reduces the dropout
voltage. The dropout in the bypass PFET equals the
load current multiplied by the on-resistance (0.25
typ)
in parallel with the buck converter and inductor dropout
resistance.
Undervoltage Loc kout (UV LO)
The MAX8500
MAX8504 do not operate with battery
voltages below the UVLO threshold of 2.35V (typ). The
output remains off until the supply voltage exceeds the
UVLO threshold. This guarantees the integrity of the
output voltage regulation.
S ync hronous Rec tific ation
An N-channel, synchronous rectifier operates during the
second half of each switching cycle (off-time). When the
inductor current falls below the N-channel current com-
parator threshold or when the PWM reaches the end of
the oscillator period, the synchronous rectifier turns off.
This prevents reverse current from the output to the
input in pulse-skipping mode. During PWM operation,
the I
LIMN
threshold adjusts to permit reverse current
during light loads. This allows regulation with a constant
switching frequency and eliminates minimum load
requirements for fixed-frequency operation.
GND
BATT
INPUT 2.6V TO5.5V
OUTPUT
1.25V TO2.5V
OR VBATT
SKIP
SHDN
REF
HP
R
C
9.1k
C
C
560pF
LX
OUT
FB
1.25V
OVER-
CURRENT
PROTECTION
PGND
COMP
10
μ
F
4.7
μ
F
4.7
μ
H
PWM
1MHz
OSC
g
m
Figure 2. MAX8504 Functional Diagram and Typical Operating Circuit
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