參數資料
型號: MAX818M
廠商: Maxim Integrated Products, Inc.
英文描述: Dual 4-Input Positive-AND Gates 20-LCCC -55 to 125
中文描述: +5V微處理器監(jiān)控電路
文件頁數: 14/16頁
文件大?。?/td> 114K
代理商: MAX818M
M
+5V Mic roproc essor S upervisory Circ uits
14
______________________________________________________________________________________
desired trip point (V
TRIP
). Resistor R3 adds hysteresis.
It will typically be an order of magnitude greater than R1
or R2. The current through R1 and R2 should be at least
1μA to ensure that the 25nA (max) PFI input leakage
current does not shift the trip point. R3 should be larger
than 200k
to prevent it from loading down the
PFO
pin.
Capacitor C1 adds additional noise rejection.
Monitoring an Additional S upply
(MAX 817/MAX 819)
The MAX817/MAX819 μP supervisors can monitor either
positive or negative supplies using a resistor voltage
divider to PFI.
PFO
can be used to generate an interrupt
to the μP or to trigger a reset (Figures 9 and 13).
Interfac ing to μPs with
Bidirec tional Reset Pins
μPs with bidirectional reset pins, such as the Motorola
68HC11 series, can contend with the MAX817/MAX818/
MAX819
RESET
output. If, for example, the
RESET
out-
put is driven high and the μP wants to pull it low, inde-
terminate logic levels may result. To correct this,
connect a 4.7k
resistor between the
RESET
output
and the μP reset I/O, as in Figure 14. Buffer the
RESET
output to other system components.
Negative-Going V
CC
T ransients
These supervisors are relatively immune to short-dura-
tion, negative-going V
CC
transients (glitches) while
issuing a reset to the μP during power-up, power-down,
and brownout conditions. Therefore, resetting the μP
when V
CC
experiences only small glitches is usually not
desirable.
The Typical Operating Characteristics show a graph of
Maximum Transient Duration vs. Reset Threshold
Overdrive for which reset pulses are
not
generated. The
graph was produced using negative-going V
CC
pulses,
starting at 3.3V and ending below the reset threshold by
the magnitude indicated (reset threshold overdrive). The
graph shows the maximum pulse width that a negative-
going V
CC
transient can typically have without triggering
a reset pulse. As the amplitude of the transient increases
(i.e., goes farther below the reset threshold), the maxi-
mum allowable pulse width decreases. Typically, a V
CC
transient that goes 100mV below the reset threshold and
lasts for 135μs will not trigger a reset pulse.
A 0.1μF bypass capacitor mounted close to the V
CC
pin provides additional transient immunity.
Figure 13. Monitoring a Negative Voltage
MAX817
MAX819
V
CC
GND
PFI
PFO
R
1
R
2
V-
NOTE: V
TRIP
IS NEGATIVE
0V
PFO
0V
V
TRIP
V-
+5V
+5V
R1
5
- 1.25
R2
1.25 - V
TRIP
=
Figure 14. Interfacing to μPs with Bidirectional Reset I/O
MAX817
MAX818
MAX819
BUFFERED RESET TOOTHER SYSTEM COMPONENTS
4.7k
V
CC
GND
V
CC
GND
RESET
RESET
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