- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384704 > MAX807 (Maxim Integrated Products, Inc.) Full-Featured レP Supervisory Circuit with 【1.5eset Accuracy PDF資料下載
參數(shù)資料
| 型號： | MAX807 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Full-Featured レP Supervisory Circuit with 【1.5eset Accuracy |
| 中文描述： | 功能完備的微處理器監(jiān)控電路，提供±1.5%的復(fù)位門限精度 |
| 文件頁數(shù)： | 10/16頁 |
| 文件大?。?/td> | 116K |
| 代理商： | MAX807 |
M
Full-Featured μP S upervisory Circ uit with
±1.5% Reset Ac c urac y
10
______________________________________________________________________________________
Watchdog Output
WDO remains high if there is a transition or pulse at
WDI during the watchdog timeout period. WDO goes
low if no transition occurs at WDI during the watchdog
timeout period. The watchdog function is disabled and
WDO is a logic high when V
CC
is below the reset
threshold or WDI is an open circuit. To generate a sys-
tem reset on every watchdog fault, simply diode-OR
connect WDO to MR (Figure 6). When a watchdog fault
occurs in this mode, WDO goes low, which pulls MR
low, causing a reset pulse to be issued. As soon as
reset is asserted, the watchdog timer clears and WDO
returns high. With WDO connected to MR, a continuous
high or low on WDI will cause 200ms reset pulses to be
issued every 1.6sec.
Chip-Enable S ignal Gating
The MAX807 provides internal gating of chip-enable
(CE) signals to prevent erroneous data from corrupting
the CMOS RAM in the event of a power failure. During
normal operation, the CE gate is enabled and passes
all CE transitions. When reset is asserted, this path
becomes disabled, preventing erroneous data from
corrupting the CMOS RAM. The MAX807 uses a series
transmission gate from the Chip-Enable Input (CE IN) to
the Chip-Enable Output (CE OUT) (Figure 1).
The 8ns max chip-enable propagation from CE IN to CE
OUT enables the MAX807 to be used with most μPs.
Chip-Enable Input
CE IN is high impedance (disabled mode) while RESET
is asserted. During a power-down sequence when V
CC
passes the reset threshold, the CE transmission gate
disables and CE IN becomes high impedance 28μs
after reset is asserted (Figure 7). During a power-up
sequence, CE IN remains high impedance (regardless
of CE IN activity) until reset is deasserted following the
reset-timeout period.
In the high-impedance mode, the leakage currents into
this input are ±1μA max over temperature. In the low-
impedance mode, the impedance of CE IN appears as
a 75
resistor in series with the load at CE OUT.
The propagation delay through the CE transmission
gate depends on both the source impedance of the
drive to CE IN and the capacitive loading on CE OUT
MR
RESET
CE IN
0V
170ns
28
μ
s TYP
1
μ
s MIN
CE OUT
V
CC
V
RST
RESET
t
WD
WDO
WDI
WDOCONNECTED TO
μ
P INTERRUPT
t
RP
Figure 4. Manual-Reset Timing Diagram
Figure 5. Watchdog Timing Relationship
V
CC
V
CC
RESET
WDO
WDO
4.7k
TO
μ
P
MR
RESET
WDI
t
RP
t
RP
t
WD
～
50
μ
s
MAX807
Figure 6. Generating a Reset on Each Watchdog Fault
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MAX807_CPE | Full-Featured レP Supervisory Circuit with 【1.5eset Accuracy |
| MAX807_CWE | Full-Featured レP Supervisory Circuit with 【1.5eset Accuracy |
| MAX807_EPE | Full-Featured レP Supervisory Circuit with 【1.5eset Accuracy |
| MAX807_EWE | Full-Featured レP Supervisory Circuit with 【1.5eset Accuracy |
| MAX807_MJE | Full-Featured レP Supervisory Circuit with 【1.5eset Accuracy |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX807_CPE | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Full-Featured レP Supervisory Circuit with 【1.5eset Accuracy |
| MAX807_CWE | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Full-Featured レP Supervisory Circuit with 【1.5eset Accuracy |
| MAX807_EPE | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Full-Featured レP Supervisory Circuit with 【1.5eset Accuracy |
| MAX807_EWE | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Full-Featured レP Supervisory Circuit with 【1.5eset Accuracy |
| MAX807_MJE | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Full-Featured レP Supervisory Circuit with 【1.5eset Accuracy |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。