• 參數(shù)資料
    型號: MAX792TMJE
    廠商: MAXIM INTEGRATED PRODUCTS INC
    元件分類: 電源管理
    英文描述: Power Supply Supervisor
    中文描述: 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, CDIP16
    封裝: CERAMIC, DIP-16
    文件頁數(shù): 12/16頁
    文件大?。?/td> 272K
    代理商: MAX792TMJE
    M
    Microprocessor and Nonvolatile
    Memory Supervisory Circuits
    12
    ______________________________________________________________________________________
    default is 1.6s. Select alternative timeout periods by
    connecting an external capacitor from SWT to GND
    (see
    Selecting an Alternative Watchdog Timeout
    sec-
    tion). When V
    CC
    is below the reset threshold, the watch-
    dog function is disabled.
    Watchdog Output
    WDO
    remains high if there is a transition or pulse at WDI
    during the watchdog timeout period. The watchdog
    function is disabled and
    WDO
    is a logic high when V
    CC
    is below the reset threshold. If a system reset is desired
    on every watchdog fault, simply diode-OR connect
    WDO
    to
    MR
    (Figure 8). When a watchdog fault occurs in this
    mode,
    WDO
    goes low, pulling
    MR
    low and causing a
    reset pulse to be issued. As soon as reset is asserted,
    the watchdog timer clears and
    WDO
    goes high. With
    WDO
    connected to
    MR
    , a continuous high or low on WDI
    will cause 200ms reset pulses to be issued every
    1.6sec (SWT connected to V
    CC
    ). When reset is not
    asserted, if no transition occurs at WDI during the
    watchdog timeout period,
    WDO
    goes low 70ns after the
    falling edge of
    WDPO
    and remains low until the next tran-
    sition at WDI (Figure 7). A single additional flip-flop can
    force the system into a hardware shutdown if there are
    two successive watchdog faults (Figure 8). When the
    MAX792/MAX820 are operated from a 5V supply,
    WDO
    has a 2 x TTL output characteristic.
    Watchdog-Pulse Output
    As described in the preceding section,
    WDPO
    can be
    used as the clock input to an external D flip-flop. Upon
    the absence of a watchdog edge or pulse at WDI at the
    end of a watchdog timeout period,
    WDPO
    will pulse low
    for 1.7ms. The falling edge of
    WDPO
    precedes
    WDO
    by
    70ns. Since
    WDO
    is high when
    WDPO
    goes low, the flip-
    flop’s Q output remains high after
    WDO
    goes low (Figure
    8). If the watchdog timer is not reset by a transition at
    WDI,
    WDO
    remains low and the next
    WDPO
    following a
    second watchdog timeout period clocks a logic low to
    the Q output, pulling
    MR
    low and causing the
    MAX792/MAX820 latch in reset. If the watchdog timer is
    reset by a transition at WDI,
    WDO
    will go high and the
    flip-flop’s Q output will remain high. Thus a system
    shutdown is only caused by two successive watchdog
    faults.
    Selecting an Alternative Watchdog Timeout Period
    The SWT input controls the watchdog timeout period.
    Connecting SWT to V
    CC
    selects the internal 1.6sec
    watchdog timeout period. Select an alternative watch-
    dog timeout period by connecting a capacitor between
    SWT and GND. Do not leave SWT floating and do not
    connect it to ground. The following formula determines
    the watchdog timeout period:
    Watchdog Timeout Period =
    k x (capacitor value in nF)ms
    where k = 27 for V
    CC
    = 3V, and k = 16.2 for V
    CC
    = 5V.
    This applies for capacitor values in excess of 4.7nF. If
    the watchdog function is unused, connect SWT to V
    CC
    .
    WDPO
    WDO
    WDI
    70ns
    1.6s
    MIN 100ns (V
    CC
    = 5V)
    MIN 300ns (V
    CC
    = 3V)
    V
    CC
    = 5V
    Figure 7. WDI,
    WDO,
    and
    WDPO
    Timing Diagram
    MAX792
    MAX820
    * FOR SYSTEM RESET ON EVERY
    WATCHDOG FAULT, OMIT THE
    FLIP-FLOP, AND DIODE
    OR
    CONNECT WDO TO MR.
    12
    GND
    3
    V
    CC
    V
    CC
    0.1
    μ
    F
    9
    MR
    4.7k
    +5V
    1
    11
    16
    RESET
    WDI
    WDPO
    0.1
    μ
    F
    15
    WDO
    μ
    P POWER
    V
    CC
    RESET
    I/O
    DCLOCK
    CLEAR
    Q
    Q
    V
    CC
    TWO
    CONSECUTIVE
    WATCHDOG
    FAULT
    INDICATION
    REACTIVATE
    *
    Figure 8. Two consecutive watchdog faults latch the system in
    reset.
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