參數(shù)資料
型號(hào): MAX780DEAP
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 電源管理
英文描述: Dual-Slot PCMCIA Analog Power Controller
中文描述: 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO20
封裝: 0.65 MM PITCH, PLASTIC, SSOP-20
文件頁數(shù): 5/12頁
文件大?。?/td> 134K
代理商: MAX780DEAP
M
Dual-S lot PCMCIA Analog Power Controller
_______________________________________________________________________________________
5
________________________________________________________Pin Desc ription
PIN
NAME
FUNCTION
1
C2
2
1
C1
3
WR
4, 5
2, 3
Logic inputs that control the voltage on AVPP.
6, 7
4, 5
Logic inputs that control the voltage on BVPP.
8, 9
6, 7
Logic inputs that control the state of the MOSFET gate drivers ADRV3 and ADRV5.
10, 11
8, 9
Logic inputs that control the state of the MOSFET gate drivers BDRV3 and BDRV5.
12, 13
10, 11
BDRV5,
BDRV3
14, 15
12, 13
ADRV5,
ADRV3
16
BGPI
17
AGPI
18
14
SHDN
15
N.C.
No connect. Not internally connected.
19
REF
1.25V reference voltage output (MAX780A and MAX780C only). Make no connection to
this pin for MAX780B.)
20
16
BVPP
Switched output that provides 0V, 5V, or 12V to the V
PP
pins of slot B.
21
17
AVPP
Switched output that provides 0V, 5V, or 12V to the V
PP
pins of slot A.
22
18
VCCIN
+5V power input
23
19
VPPIN
+12V power input. VPPIN can have 0V or 5V applied as long as VCCIN = 5V.
24
20
GND
Ground
MAX780A/B/C
Pin-strap input that selects edge-triggered register or direct digital inputs. Tying C2 to
VCCIN makes the logic inputs edge triggered; inputs to pins 4-11 are clocked in on the
rising edge of
WR
. Tying C2 to GND allows control signals to be directly applied to the
logic inputs on pins 4-11. Connect to GND for MAX780C.
Pin-strap input that selects one of two logic decode modes for the digital inputs. See Tables 1-3.
Logic-level power-ready output that stays low as long as BVPP is greater than 11.05V
(MAX780A and MAX780C only). Make no connection to this pin for MAX780B.
Logic-level power-ready output that stays low as long as AVPP is greater than 11.05V
(MAX780A and MAX780C only). Make no connection to this pin for MAX780B.
Logic input that shuts the MAX780 down to a low supply-current state when brought
low. Asserting
SHDN
forces ADRV3, BDRV3, ADRV5, BDRV5, REF,
AGPI
, and
BGPI
low. All V
PP
inputs and outputs are functional for either state of
SHDN
. Program AVPP
and BVPP to 0V for lowest power consumption.
Write pulse input. When C2 is tied to VCCIN, a rising edge on
WR
clocks in the V
CC
and V
PP
enables. When C2 is tied to GND, inputs to
WR
have no effect. Connect to
GND for MAX780C.
AVCC1,
AVCC0
BVCC1,
BVCC0
AVPP1,
AVPP0
BVPP1,
BVPP0
Open-drain gate driver outputs that control the MOSFETs that switch the V
CC
pin of slot
B to 0V, 3.0V/3.3V, or 5V.
MAX780D
Open-drain gate driver outputs that control the MOSFETs that switch the V
CC
pin of slot
A to 0V, 3.0V/3.3V, or 5V.
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