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參數(shù)資料
| 型號： | MAX7651ECB |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | Flash Programmable 12-Bit Integrated Data-Acquisition Systems |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, MO-136BJ, TQFP-64 |
| 文件頁數(shù)： | 20/36頁 |
| 文件大小： | 479K |
| 代理商： | MAX7651ECB |
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M
Flash Programmable 12-Bit Integrated
Data-Acquisition Systems
20
______________________________________________________________________________________
are unique to the MAX7651/MAX7652. Subsequent
sections of this data sheet explain the SFR functions.
RESERVED SFR addresses are used for MAX7651/
MAX7652 testing and should not be accessed by user
software. Undesignated SFR addresses are not imple-
mented and will return indefinite data when read.
Special Function Registers for
Microprocessor Operations and Control
Accumulator SFR
The Accumulator SFR is used for arithmetic operations
including addition, subtraction, multiplication, division,
and Boolean bit manipulation. Accumulator specific
instructions designate the accumulator as
“
A
”
.
B SFR
The B SFR is used for multiply and divide operations. It
is otherwise available as a scratchpad register.
Program Status Word SFR
The PSW or Program Status Word SFR contains bits
that indicate the state of the microprocessor CPU.
Table 6 shows the individual bit functions.
Stack Pointer SFR
The SP or Stack Pointer SFR contains the
“
top-of-the-
stack
”
address in internal RAM. This address incre-
ments before data is stored during PUSH and CALL
executions. The default value is 07H after reset, so that
the stack begins at 08H.
Dual Data Pointer SFRs
The MAX7651/MAX7652 feature dual data pointers to
enhance execution times when moving large blocks of
data. All DPTR-related instructions use 16 bits con-
tained at SFR pairs DPH0 and DPL0 or DPH1 and DPL1
to address external data RAM or peripherals. Bit 0
(SEL) within the DPS SFR determines the data pointer.
No other bits have significance in this register. When
SEL= 0, DPTR instructions use DPH0 and DPL0, when
SEL=1, DPTR instructions use DPH1 and DPL1.
Program code developed for 8051 platforms that use a
single data pointer (DPH0 and DPL0) requires no modi-
fication if SEL = 0 (the default value).
Power Control SFR
The PCON Power Control SFR provides software con-
trol over the power modes. In both IDLE and STOP
modes, CPU processing is suspended and internal
registers maintain their current data. The STOP mode
additionally disables the internal clock and analog cir-
cuitry. Any enabled CPU interrupt can be used to termi-
nate the IDLE mode. A reset is necessary to terminate
the STOP mode and is sufficient to terminate the IDLE
mode. Table 7 shows the PCON SFR format.
Instruction Set
The MAX7651/MAX7652 instruction set is compatible with
the 8051 industry standard. See the MAX7651/ MAX7652
Programmer
’
s Reference Manual
for a complete listing.
Analog-to-Digital Converter
ADC Operation
Figure 6 shows a simplified model of the converter
input structure and the associated switch timing. Once
initiated, a voltage conversion requires 224 periods of
the external master clock. Capacitor C
HOLD
charges to
the difference between inputs AIN+ and AIN- during
eight clock periods of acquisition time that begin on the
rising edge of clock cycle 13. This charge sample is
subsequently transferred to the ADC (through the
action of SW5) during eight clock periods that begin on
the rising edge of clock cycle 21. The ADC asserts a
conversion complete flag on the rising-edge of clock
cycle 225 (see
ADC Special Function Registers
).
REGISTER
ACC
EIE
EEAL
EEAH
EEDAT
EESTCMD
B
EIP
PWMC
ADDRESS
E0
E8
EA
EB
EC
ED
F0
F8
FE
BIT 7
0
1
0
0
0
0
0
1
0
BIT 6
0
1
0
0
0
0
0
1
0
BIT 5
0
1
0
0
0
0
0
1
0
BIT 4
0
0
0
0
0
0
0
0
0
BIT 3
0
0
0
0
0
0
0
0
0
BIT 2
0
0
0
0
0
0
0
0
0
BIT 1
0
0
0
0
0
0
0
0
0
BIT 0
0
0
0
0
0
0
0
0
0
Table 5. SFR Contents on Power-Up or Reset (continued)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MAX7652CCB | Flash Programmable 12-Bit Integrated Data-Acquisition Systems |
| MAX7652ECB | Flash Programmable 12-Bit Integrated Data-Acquisition Systems |
| MAX766ESA | -5V/-12V/-15V or Adjustable, High-Efficiency, Low IQ DC-DC Inverters |
| MAX765 | -5V/-12V/-15V or Adjustable, High-Efficiency, Low IQ DC-DC Inverters |
| MAX764-MAX766 | -5V/-12V/-15V or Adjustable, High-Efficiency, Low IQ DC-DC Inverters |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX7651EVKIT | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: |
| MAX7652CCB | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: |
| MAX7652ECB | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: |
| MAX765C/D | 功能描述:直流/直流開關(guān)調(diào)節(jié)器 -12V or Adjustable High-Efficiency Low IQ DC-DC Inverters RoHS:否 制造商:International Rectifier 最大輸入電壓:21 V 開關(guān)頻率:1.5 MHz 輸出電壓:0.5 V to 0.86 V 輸出電流:4 A 輸出端數(shù)量: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFN 4 x 5 |
| MAX765C/D DIE | 制造商:Maxim Integrated Products 功能描述: |
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