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參數(shù)資料
| 型號(hào)： | MAX745 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | 8-Bit Parallel-Out Serial Shift Registers 14-CFP -55 to 125 |
| 中文描述： | 開關(guān)模式鋰離子電池充電器 |
| 文件頁(yè)數(shù)： | 6/8頁(yè) |
| 文件大?。?/td> | 91K |
| 代理商： | MAX745 |
M
S witc h-Mode Lithium-Ion
Battery Charger
6
_______________________________________________________________________________________
V
REF
/ 2, the voltage limit is 4.2V. Table 1 defines the
battery cell count.
The battery limit voltage is set by the following:
Solving for V
ADJ
, we get:
Set V
ADJ
by choosing a value for R11 (typically 100k),
and determine R3 by:
R3 = [1 - (V
ADJ
/ V
REF
)] x R11 (Figure 1)
where V
REF
= 4.2V and cell count is 1, 2, 3, or 4
(Table 1).
The voltage-regulation loop is compensated at the CCV
pin. Typically, a series-resistor-capacitor combination
can be used to form a pole-zero doublet. The pole
introduced rolls off the gain starting at low frequencies.
The zero of the doublet provides sufficient AC gain at
mid-frequencies. The output capacitor (C1) rolls off the
mid-frequency gain to below unity. This guarantees sta-
bility before encountering the zero introduced by the
C1’s equivalent series resistance (ESR). The GMV
amplifier’s output is internally clamped to between one-
fourth and three-fourths of the voltage at REF.
Current Control
The charging current is set by a combination of the cur-
rent-sense resistor value and the SETI pin voltage. The
current-sense amplifier measures the voltage across
the current-sense resistor, between CS and BATT. The
current-sense amplifier’s gain is 6. The voltage on SETI
is buffered and then divided by 4. This voltage is com-
pared to the current-sense amplifier’s output.
Therefore, full-scale current is accomplished by con-
necting SETI to REF. The full-scale charging current
(I
FS)
is set by the following:
I
FS
= 185mV / R1 (Figure 1)
V
= 9.523 V
cell count
(
9.023V
ADJ
BATT
REF
)
V
= cell count x V
V
1
2V
9.523
BATT
REF
ADJ
REF
+
CELL0
GND
VL
GND
VL
CELL1
GND
GND
VL
VL
1
2
3
4
CELL COUNT
REF
(UP TO24V)
VL
DCIN
V
IN
BST
DHI
DLO
LX
PGND
CS
BATT
THM 1
VADJ
SETI
CCI
C3
47nF
R11
100k
1%
R3
100k
1%
R16
D2
C6
0.1
μ
F
C7
0.1
μ
F
M1A
1/2 IRF7303
1/2 IRF7303
M1B
D6
MBRS
340T3
D1
MBRS
340T3
0.2
R1
C1
68
μ
F
L1
22
μ
H
IN4148
R12
R15
10k
C4
0.1
μ
F
C5
4.7
μ
F
R2
10k
C2, 0.1μF
GND
IBAT
CCV
MAX745
BATTERY
THM/SHDN
STATUS
Figure 1. Standard Application Circuit
Table 1. Cell-Count Programming Table
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