參數(shù)資料
型號(hào): MAX7456EVKIT+
廠(chǎng)商: Maxim Integrated Products
文件頁(yè)數(shù): 18/44頁(yè)
文件大?。?/td> 0K
描述: KIT EVAL FOR MAX7456
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
主要目的: 視頻,屏幕顯示器(OSD)
嵌入式: 是,MCU,16 位
已用 IC / 零件: MAX7456
主要屬性: NTSC/PAL 單通道單色屏幕顯示器(OSD),帶集成視頻驅(qū)動(dòng)器
次要屬性: GUI,SPI 接口
已供物品:
產(chǎn)品目錄頁(yè)面: 1424 (CN2011-ZH PDF)
Video Mode 0 Register (VM0)
Write address = 00H, read address = 80H.
Read/write access: unrestricted.
To write to this register, the following conditions must
be met:
1) STAT[5] = 0, the character memory (NVM) is not
busy.
2) DMM[2] = 0, the display memory (SRAM) is not
in the process of being cleared.
Single-Channel Monochrome On-Screen
Display with Integrated EEPROM
BIT
DEFAULT
FUNCTION
7
0
Don’t Care
60
Video Standard Select
0 = NTSC
1 = PAL
5, 4
00
Sync Select Mode (Table 1)
0x = Autosync select (external sync when LOS = 0 and internal sync when LOS = 1)
10 = External
11 = Internal
30
Enable Display of OSD Image
0 = Off
1 = On
20
Vertical Synchronization of On-Screen Data
0 = Enable on-screen display immediately
1 = Enable on-screen display at the next VSYNC
10
Software Reset Bit
When this bit is set, all registers are set to their default values and the display memory is cleared.
When a stable 27MHz clock is present, this bit is automatically cleared internally after typically
100s. The user does not need to write a 0 afterwards. SPI operations should not be performed
during this time or unpredictable results may occur. The status of the bit can be checked by
reading this register after typically 100s. This register is not accessible for writing until the display
memory clear operation is finished (typically 20s).
00
Video Buffer Enable
0 = Enable
1 = Disable (VOUT is high impedance)
X = Don’t care.
MAX7456
Maxim Integrated
25
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