參數(shù)資料
型號: MAX7432
廠商: Maxim Integrated Products, Inc.
英文描述: Quadruple 2-Line To 1-Line Data Selectors/Multiplexers 20-LCCC -55 to 125
中文描述: 標(biāo)準清晰度、視頻重建濾波器及緩沖器
文件頁數(shù): 10/21頁
文件大小: 444K
代理商: MAX7432
M
Standard Definition Video Reconstruction
Filters and Buffers
10
______________________________________________________________________________________
CLEVEL:
Clamp Level bit. A logic 0 selects a clamp
level of 1V while a logic 0 selects a clamp level of 1.5V
at the output.
[BOOST1, BOOST0]:
High-Frequency Boost Control bits.
The adjust bits select the amount of high-frequency boost
for the filter. Table 2 defines four levels of adjustment.
OUTDISABLE:
Output Disable bit. A logic 0 selects
normal operation while a logic 1 places the output in a
high-impedance state.
MAX7430 Control Register
Table 3 defines the structure of the MAX7430 16-bit con-
trol register programmed by MSPB. This register controls
the selection of IN_A or IN_B, selection of filter 1 or 2, filter
bypassing, clamp-level selection, high-frequency boost
control, and output disable. See
Maxim
s Single Pin Bus
Interface (MSPB)
section for detailed programming
instructions.
ABSEL_:
Channel Select bit. A logic zero selects the
input at IN_B to be processed while a logic 1 selects
the input at IN_A to be processed.
BYPASS_:
Filter Bypass Select bit. A logic 1 selects
the channel filter while a logic 0 bypasses the channel
filter.
CLEVEL_:
Clamp Level bit. A logic 0 selects a channel
clamp level of 1V while a logic 0 selects a channel
clamp level of 1.5V at the output.
[BOOST1_, BOOST0_]:
High-Frequency Boost Control
bits. The adjust bits select the amount of high-frequency
boost for the channel filter. Table 4 defines four levels of
adjustment.
OUTDISABLE_:
Output Disable bit. A logic 0 selects
normal channel output operation while a logic 1 puts
the channel output in a high-impedance state.
MAX7432 Control Register
Table 5 defines the structure of the MAX7432 24-bit
control register programmed by MSPB. This register
controls the selection of IN_A or IN_B, selection of filter
1, 2, or 3, filter bypassing, clamp-level selection, high-
frequency boost control, and output disable. See
Maxim
s Single Pin Bus Interface (MSPB)
section for
detailed programming instructions.
ABSEL_:
Channel Select bit. A logic zero selects the
input at IN_B to be processed while a logic 1 selects
the input at IN_A to be processed.
BYPASS_:
Filter Bypass Select bit. A logic 1 selects
the channel filter while a logic 0 bypasses the channel
filter.
CLEVEL_:
Clamp Level bit. A logic 0 selects a channel
clamp level of 1V while a logic 0 selects a channel
clamp level of 1.5V at the output.
[BOOST1_, BOOST0_]:
High-Frequency Boost Control
bits. The adjust bits select the amount of high-frequency
boost for the channel filter. Table 6 defines four levels of
adjustment.
OUTDISABLE_:
Output Disable Bit. A logic 0 selects
normal channel output operation while a logic 1 puts
the channel output in high-impedance state.
(MSB)
NAME
ABSEL2
BYPASS2
CLEVEL2
BOOST1(2)
BOOST0(2)
OUT
DISABLE2
DEFAULT
0
1
1
0
0
0
0
0
NAME
ABSEL1
BYPASS1
CLEVEL1
BOOST1(1)
BOOST0(1)
OUT
DISABLE1
0
DEFAULT
0
1
1
0
0
0
0
FIRST BIT
(LSB)
Table 3. MAX7430 Control Register
BOOST1_
BOOST0_
RELATIVE HIGH-
FREQUENCY BOOST
0
0
1
1
0
1
0
1
0
0.45dB
0.90dB
1.35dB
Table 4. Boost Level Programming
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