參數(shù)資料
型號(hào): MAX7387CMVB
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 電源管理
英文描述: System Monitoring Oscillator with Watchdog and Power Fail
中文描述: 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO10
封裝: 3 X 3 MM, MO-187CBA, MICRO, SOP-10
文件頁(yè)數(shù): 13/14頁(yè)
文件大?。?/td> 680K
代理商: MAX7387CMVB
VCC
CLK
RST
INTERNAL
WATCHDOG STATE
WDI
WDO
ACTIVE
TRIPPED
RESET TIMEOUT PERIOD
(tRST)
WATCHDOG TIMEOUT
PERIOD (tWDG)
Figure 2. Watchdog Timing Diagram
MAX7387/MAX7388
System Monitoring Oscillator with
Watchdog and Power Fail
8
_______________________________________________________________________________________
circuits are reset and the watchdog timer restarts at the
end of the reset cycle (RST/RST output releases).
For the MAX7387, the WDO output asserts if the WDI
input does not receive a rising edge within the watchdog
timeout period. WDO output remains asserted until a
valid edge is received on the WDI input, signifying cor-
rect microprocessor operation. The WDO output can be
used as a status indicator either to the microprocessor
or to an external device, such as a fault-indicating LED
or sounder. The WDO output is an open-drain output.
The power-up condition of the WDO output is high
(not asserted).
The operation of the watchdog and reset function is
illustrated in Figure 2.
The watchdog timeout period is set to one of nine possible
values by pin strapping WDS1 and WDS2. Each control
input has three possible values assigned by connection
to GND, VCC, or VCC/2 (see Table 1). One of the
assigned values disables the watchdog function and is
intended for customer use during test. The watchdog
timer is disabled while the RST/RST output is asserted.
Power Fail
MAX7388 Power Fail
The power-fail function provides early warning of a power
failure. The power-fail comparator threshold is internally
set to 4.38V VCC rising threshold (VITH). The open-drain
PFO asserts low if the VCC supply voltage drops below
the VCC falling threshold value. The VCC falling threshold
is nominally 2% below the VCC rising threshold.
MAX7387 Power Fail
Internal (VCC) detection is configured by connecting
PFI to VCC. The internal VCC rising threshold (VITH) is
set at 4.38V. The open-drain PFO asserts low if the VCC
supply voltage drops below the VCC falling threshold
value (VHYST). The VCC falling threshold is nominally
2% below the VCC rising threshold.
Applications Information
Interfacing to a Microcontroller
Clock Input
The CLOCK output is a push-pull, CMOS logic output,
which directly drives any microprocessor (P) or micro-
controller (C) clock input. There are no impedance-
Table 1. Watchdog Timeout Periods
WATCHDOG TIMEOUT
PERIOD (ms)
WDS1
WDS2
MIN
TYP
MAX
GND
11
16
22
VCC/2 = open
GND
22
32
44
VCC
GND
44
64
88
GND
VCC/2 = open
88
128
177
VCC/2 = open
177
256
354
VCC
VCC/2 = open
354
512
708
GND
VCC
708
1024
1416
VCC/2 = open
VCC
1416
2048
2832
VCC
Disabled
Note: WDS1 or WDS2 is pulled to open if left floating.
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參數(shù)描述
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MAX7387CMWB 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
MAX7387CMWB-T 制造商:Maxim Integrated Products 功能描述:SYSTEM MONITORING OSCILLATOR WITH W - Tape and Reel
MAX7387CSAC 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
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