I2C Port Expander with Eight Push-Pull Outputs _________________________" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� MAX7320AEE+T
寤犲晢锛� Maxim Integrated Products
鏂囦欢闋佹暩(sh霉)锛� 8/14闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC I/O EXPANDER I2C 8B 16QSOP
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 2,500
鎺ュ彛锛� I²C
杓稿叆/杓稿嚭鏁�(sh霉)锛� 8
涓柗杓稿嚭锛� 鐒�
闋荤巼 - 鏅�(sh铆)閻橈細 400kHz
闆绘簮闆诲锛� 1.71 V ~ 5.5 V
宸ヤ綔婧害锛� -40°C ~ 125°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 16-SSOP锛�0.154"锛�3.90mm 瀵級
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 16-QSOP
鍖呰锛� 甯跺嵎 (TR)
鍖呮嫭锛� POR
MAX7320
I2C Port Expander with Eight Push-Pull Outputs
_______________________________________________________________________________________
3
PORT AND TIMING CHARACTERISTICS
(V+ = +1.71V to +5.5V, TA = -40掳C to +125掳C, unless otherwise noted. Typical values are at V+ = +3.3V, TA = +25掳C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Port Output Data Valid
tPPV
CL
鈮� 100pF
4
s
TIMING CHARACTERISTICS
(V+ = +1.71V to +5.5V, TA = -40掳C to +125掳C, unless otherwise noted. Typical values are at V+ = +3.3V, TA = +25掳C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Serial Clock Frequency
fSCL
400
kHz
Bus Free Time Between a STOP
and a START Condition
tBUF
1.3
s
Hold Time (Repeated) START
Condition
tHD, STA
0.6
s
Repeated START Condition
Setup Time
tSU, STA
0.6
s
STOP Condition Setup Time
tSU, STO
0.6
s
Data Hold Time
tHD, DAT
(Note 3)
0.9
s
Data Setup Time
tSU, DAT
100
ns
SCL Low to Data Out Valid
tVD, DAT
SCL low to SDA output valid
3.4
s
SCL Clock Low Period
tLOW
1.3
s
SCL Clock High Period
tHIGH
0.7
s
Rise Time of Both SDA and SCL
Signals, Receiving
tR
(Notes 2, 4)
20 +
0.1Cb
300
ns
Fall Time of Both SDA and SCL
Signals, Receiving
tF
(Notes 2, 4)
20 +
0.1Cb
300
ns
Fall Time of SDA Transmitting
tF,TX
(Notes 2, 4)
20 +
0.1Cb
250
ns
Pulse Width of Spike Suppressed
tSP
(Note 5)
50
ns
Capacitive Load for Each Bus
Line
Cb
(Note 2)
400
pF
RST Pulse Width
tW
500
ns
RST Rising to START Condition
Setup Time
tRST
1s
Note 1: All parameters tested at TA = +25掳C. Specifications over temperature are guaranteed by design.
Note 2: Guaranteed by design.
Note 3: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) to bridge
the undefined region of SCL鈥檚 falling edge.
Note 4: Cb = total capacitance of one bus line in pF. tR and tF measured between 0.3 x V+ and 0.7 x V+, ISINK
鈮� 6mA.
Note 5: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
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MAX7320ATE-T 鍔熻兘鎻忚堪:鎺ュ彛-I/O鎿�(ku貌)灞曞櫒 RoHS:鍚� 鍒堕€犲晢:NXP Semiconductors 閭忚集绯诲垪: 杓稿叆/杓稿嚭绔暩(sh霉)閲�: 鏈€澶у伐浣滈牷鐜�:100 kHz 宸ヤ綔闆绘簮闆诲:1.65 V to 5.5 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:HVQFN-16 灏佽:Reel
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