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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | MAX7316AEE+ |
| 寤犲晢锛� | Maxim Integrated Products |
| 鏂囦欢闋佹暩(sh霉)锛� | 23/24闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC I/O EXPANDER I2C 16B 16QSOP |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 100 |
| 鎺ュ彛锛� | I²C锛孲M 绺界窔 |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 10 |
| 涓柗杓稿嚭锛� | 鏄� |
| 闋荤巼 - 鏅傞悩锛� | 400kHz |
| 闆绘簮闆诲锛� | 2 V ~ 3.6 V |
| 宸ヤ綔婧害锛� | -40°C ~ 125°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 16-SSOP锛�0.154"锛�3.90mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 16-QSOP |
| 鍖呰锛� | 绠′欢 |
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MAX7316
Serial Interface
Serial Addressing
The MAX7316 operates as a slave that sends and
receives data through an I2C-compatible 2-wire inter-
face. The interface uses a serial data line (SDA) and a
serial clock line (SCL) to achieve bidirectional commu-
nication between master(s) and slave(s). A master (typ-
ically a microcontroller) initiates all data transfers to and
from the MAX7316 and generates the SCL clock that
synchronizes the data transfer (Figure 2).
The MAX7316 SDA line operates as both an input and
an open-drain output. A pullup resistor, typically 4.7k
惟,
is required on SDA. The MAX7316 SCL line operates
only as an input. A pullup resistor, typically 4.7k
惟, is
required on SCL if there are multiple masters on the 2-
wire interface, or if the master in a single-master system
has an open-drain SCL output.
Each transmission consists of a START condition
(Figure 3) sent by a master, followed by the MAX7316
7-bit slave address plus R/W bit, a register address
byte, one or more data bytes, and finally a STOP condi-
tion (Figure 3).
Start and Stop Conditions
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, it issues a
STOP (P) condition by transitioning SDA from low to
high while SCL is high. The bus is then free for another
transmission (Figure 3).
Bit Transfer
One data bit is transferred during each clock pulse.
The data on SDA must remain stable while SCL is high
(Figure 4).
Acknowledge
The acknowledge bit is a clocked 9th bit that the recipi-
ent uses to handshake receipt of each byte of data
(Figure 5). Thus, each byte transferred effectively
requires 9 bits. The master generates the 9th clock
pulse, and the recipient pulls down SDA during the
acknowledge clock pulse so the SDA line is stable low
during the high period of the clock pulse. When the
master is transmitting to the MAX7316, the device gen-
erates the acknowledge bit because the MAX7316 is
the recipient. When the MAX7316 is transmitting to the
master, the master generates the acknowledge bit
because the master is the recipient.
Slave Address
The MAX7316 has a 7-bit long slave address (Figure 6).
The eighth bit following the 7-bit slave address is the
R/W bit. The R/W bit is low for a write command, high
for a read command.
10-Port I/O Expander with LED Intensity
Control, Interrupt, and Hot-Insertion Protection
8
_______________________________________________________________________________________
Figure 3. Start and Stop Conditions
SDA
SCL
START
CONDITION
STOP
CONDITION
SP
Figure 4. Bit Transfer
SDA
SCL
DATA LINE STABLE;
DATA VALID
CHANGE OF DATA
ALLOWED
Figure 5. Acknowledge
SCL
SDA BY
TRANSMITTER
CLOCK PULSE
FOR ACKNOWLEDGE
START
CONDITION
SDA BY
RECEIVER
12
89
S
Figure 6. Slave Address
SDA
SCL
1
MSB
LSB
ACK
00
A6
0
A2
R/W
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| ATMEGA8515L-8MUR | MCU AVR 8KB FLASH 8MHZ 44QFN |
| MAX7316ATE+ | IC I/O EXPANDER I2C 16B 16TQFN |
| ATMEGA8515-16MUR | MCU AVR 8KB FLASH 16MHZ 44QFN |
| MAX7315ATE+T | IC I/O EXPANDER I2C 8B 16TQFN-EP |
| MAX7315AUE+T | IC I/O EXPANDER I2C 8B 16TSSOP |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| MAX7316AEE+ | 鍔熻兘鎻忚堪:鎺ュ彛-I/O鎿�(ku貌)灞曞櫒 10-Bit I/O Port Expander RoHS:鍚� 鍒堕€犲晢:NXP Semiconductors 閭忚集绯诲垪: 杓稿叆/杓稿嚭绔暩(sh霉)閲�: 鏈€澶у伐浣滈牷鐜�:100 kHz 宸ヤ綔闆绘簮闆诲:1.65 V to 5.5 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:HVQFN-16 灏佽:Reel |
| MAX7316AEE+T | 鍔熻兘鎻忚堪:鎺ュ彛-I/O鎿�(ku貌)灞曞櫒 10-Bit I/O Port Expander RoHS:鍚� 鍒堕€犲晢:NXP Semiconductors 閭忚集绯诲垪: 杓稿叆/杓稿嚭绔暩(sh霉)閲�: 鏈€澶у伐浣滈牷鐜�:100 kHz 宸ヤ綔闆绘簮闆诲:1.65 V to 5.5 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:HVQFN-16 灏佽:Reel |
| MAX7316AEE-T | 鍔熻兘鎻忚堪:鎺ュ彛-I/O鎿�(ku貌)灞曞櫒 10-Bit I/O Port Expander RoHS:鍚� 鍒堕€犲晢:NXP Semiconductors 閭忚集绯诲垪: 杓稿叆/杓稿嚭绔暩(sh霉)閲�: 鏈€澶у伐浣滈牷鐜�:100 kHz 宸ヤ綔闆绘簮闆诲:1.65 V to 5.5 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:HVQFN-16 灏佽:Reel |
| MAX7316ATE | 鍔熻兘鎻忚堪:鎺ュ彛-I/O鎿�(ku貌)灞曞櫒 10-Bit I/O Port Expander RoHS:鍚� 鍒堕€犲晢:NXP Semiconductors 閭忚集绯诲垪: 杓稿叆/杓稿嚭绔暩(sh霉)閲�: 鏈€澶у伐浣滈牷鐜�:100 kHz 宸ヤ綔闆绘簮闆诲:1.65 V to 5.5 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:HVQFN-16 灏佽:Reel |
| MAX7316ATE+ | 鍔熻兘鎻忚堪:鎺ュ彛-I/O鎿�(ku貌)灞曞櫒 10-Bit I/O Port Expander RoHS:鍚� 鍒堕€犲晢:NXP Semiconductors 閭忚集绯诲垪: 杓稿叆/杓稿嚭绔暩(sh霉)閲�: 鏈€澶у伐浣滈牷鐜�:100 kHz 宸ヤ綔闆绘簮闆诲:1.65 V to 5.5 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:HVQFN-16 灏佽:Reel |
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