參數(shù)資料
型號: MAX7312AUG
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 微控制器/微處理器
英文描述: 4-Bit D-type Registers with 3-State Outputs 16-CDIP -55 to 125
中文描述: 16 I/O, PIA-GENERAL PURPOSE, PDSO24
封裝: 4.40 MM, MO-153AD, TSSOP-24
文件頁數(shù): 8/17頁
文件大?。?/td> 373K
代理商: MAX7312AUG
M
MAX7312 generates the acknowledge bit since the
MAX7312 is the recipient. When the MAX7312 is trans-
mitting to the master, the master generates the
acknowledge bit.
Slave Address
The MAX7312 has a 7-bit-long slave address (Figure 6).
The 8th bit following the 7-bit slave address is the R/
W
bit. Set this bit low for a write command and high for a
read command.
Slave address pins AD2, AD1, and AD0 choose 1 of 64
slave ID addresses (Table 7).
Data Bus Transaction
The command byte is the first byte to follow the 8-bit
device slave address during a write transmission
(Table 1, Figure 7). The command byte is used to deter-
mine which of the following registers are written or read.
Writing to Port Registers
Transmit data to the MAX7312 by sending the device
slave address and setting the LSB to a logic zero. The
command byte is sent after the address and deter-
mines which registers receive the data following the
command byte (Figure 7).
2-Wire-Interfaced 16-Bit I/O Port Expander
with Interrupt and Hot-Insertion Protection
8
_______________________________________________________________________________________
SDA
SDA
A6
MSB
A5
A4
A3
A2
A1
A0
LSB
ACK
R/W
PROGRAMMABLE
Figure 6. Slave Address
Table 1. Command Byte Register
COMMAND BYTE
ADDRESS (HEX)
FUNCTION
PROTOCOL
POWER-UP
DEFAULT
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0xFF
Input port 1
Input port 2
Output port 1
Output port 2
Port 1 polarity inversion
Port 2 polarity inversion
Port 1 configuration
Port 2 configuration
Timeout register
Factory reserved. (Do not write to this register.)
Read byte
Read byte
Read/write byte
Read/write byte
Read/write byte
Read/write byte
Read/write byte
Read/write byte
Read/write byte
XXXX XXXX
XXXX XXXX
1111 1111
1111 1111
0000 0000
0000 0000
1111 1111
1111 1111
0000 0001
1
2
3
4
5
6
7
8
9
SCL
SDA
S
A
0
0
0
0
0
0
1
7
6
5
4
3
2
1
0
A
7
6
5
4
3
2
1
0
A
0
A
SLAVE ADDRESS
COMMAND BYTE
PORT 1 DATA
PORT 2 DATA
R/W
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM SLAVE
START
CONDITION
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM SLAVE
t
PV
t
PV
WRITE TO PORT
DATA OUT PORT 1
READ FROM PORT 2
Figure 7. Writes to Output Registers Through Write Byte Protocol
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