參數(shù)資料
型號(hào): MAX707ESA-T
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類(lèi): 電源管理
英文描述: Analog IC
中文描述: 2-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8
封裝: SO-8
文件頁(yè)數(shù): 8/12頁(yè)
文件大?。?/td> 84K
代理商: MAX707ESA-T
MAX707, MAX708
http://onsemi.com
8
RESET Signal Integrity During Power–Down
The MAX707/708 RESET output is valid until V
CC
falls
below 1.0 V. Then, the output becomes an open circuit and
no longer sinks current. This means CMOS logic inputs of
the P will be floating at an undetermined voltage. Most
digital systems are completely shutdown well above this
voltage. However, in the case RESET must be maintained
valid to V
CC
= 0 V, a pull down resistor must be connected
from RESET to ground to discharge stray capacitances and
hold the output low (Figure 14). This resistor value, though
not critical, should be chosen large enough not to load
RESET and small enough to pull it to ground. R = 100 k
will be suitable for most applications.
RESET
Figure 14. Ensuring RESET Valid to V
CC
= 0 V
VCC
GND
MAX707/708
R
100 K
Interfacing with Ps with Bidirectional I/O Pins
Some Ps (such as Motorola 68HC11) have bidirectional
reset pins. If, for example, the RESET output is driven high
and the P wants to put it low, indeterminate logic level may
result. This can be avoided by adding a 4.7 k
resistor in
series with the output of the MAX707/708 (Figure 15). If
there are other components in the system that require a reset
signal, they should be buffered so as not to load the reset line.
If the other components are required to follow the reset I/O
of the P, the buffer should be connected as shown with the
solid line.
RESET
RESET
Figure 15. Interfacing to Bidirectional Reset I/O
GND
MAX707/708
VCC
GND
VCC
BUFFER
4.7 K
P
BUFFERED
RESET TO
OTHER SYSTEM
COMPONENTS
Monitoring Additional Supply Levels
When connecting a voltage divider to PFI and adjusting it
properly, you can monitor a voltage different than the
unregulated DC one. As shown in Figure 16, to increase
noise immunity, hysteresis may be added to the power–fail
comparator just by a resistor between PFO and PFI. Not to
unbalance the potential divider network, R3 should be 10
times the sum of the two resistors R1 and R2. If required, a
capacitor between PFI and GND will reduce the sensitivity
of the circuit to high–frequency noise on the line being
monitored. The PFO output may be connected to MR input
to generate a low level on the RESET when Vcc_1 drops out
of tolerance. Thus a RESET is generated when one of the
two voltages is below its threshold level.
MAX707/708
Figure 16. Monitoring Additional Supply Levels
GND
VCC
GND
VCC
P
RESET
MR
PFO
PFI
RESET
R1
R2
R3
V
CC_1
V
CC_2
V
CC_3
PFO
V
CC_1
V
CC_2
0 V
0 V
V
L
V
H
VL
1.25
R1
1.25
R2
1.25
Vcc_2
R3
VH
1.25
(1
R1
R2
R2
R3
R3
)
VHYS
VH
VL
R1
Vcc_2
R3
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