參數(shù)資料
型號(hào): MAX7033EUI
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Quadruple 2-Line To 1-Line Data Selectors/Multiplexers 20-LCCC -55 to 125
中文描述: SPECIALTY TELECOM CIRCUIT, PDSO28
封裝: 4.40 MM, MO-153AE, TSSOP-28
文件頁(yè)數(shù): 8/16頁(yè)
文件大?。?/td> 849K
代理商: MAX7033EUI
M
315MHz/433MHz ASK Superheterodyne
Receiver with AGC Lock
8
_______________________________________________________________________________________
Pin Description
PIN
TSSOP
1
THIN QFN
29
NAME
FUNCTION
XTAL1
Crystal Input 1 (See the
Phase-Locked Loop
section)
Positive Analog Supply Voltage. For +5V operation, AV
DD
is connected to an on-chip +3.2V
low-dropout regulator. Both AV
DD
pins must be externally connected to each other. Bypass
each pin to AGND with a 0.01μF capacitor as close to the pin as possible (see the
Typical
Application Circuit
).
Low-Noise Amplifier Input (See the
Low-Noise Amplifier
section)
2, 7
4, 30
AV
DD
3
31
LNAIN
4
32
LNASRC
Low-Noise Amplifier Source for External Inductive Degeneration. Connect inductor to ground
to set the LNA input impedance (see the
Low-Noise Amplifier
section).
5, 10
2, 7
AGND
Analog Ground
6
3
LNAOUT
Low-Noise Amplifier Output. Connect to mixer input through an LC tank filter (see the
Low-
Noise Amplifier
section).
8
9
5
6
MIXIN1
MIXIN2
1st Differential Mixer Input. Connect to LC tank filter from LNAOUT.
2nd Differential Mixer Input. Connect through a 100pF capacitor to AV
DD
side of the LC tank.
11
8
IRSEL
Image-Rejection Select. Set V
IRSEL
= 0V to center image rejection at 315MHz. Leave IRSEL
unconnected to center image rejection at 375MHz. Set V
IRSEL
= V
DD5
to center image
rejection at 433MHz.
12
13
9
10
MIXOUT
DGND
330
Mixer Output. Connect to the input of the 10.7MHz bandpass filter.
Digital Ground
14
11
DV
DD
Positive Digital Supply Voltage. Connect to AV
DD
. Bypass to DGND with a 0.01μF capacitor
as close to the pin as possible.
15
12
AC
Automatic Gain Control. See Figure 1. Internally pulled down to AGND with a 100k
resistor.
Crystal Divider Ratio Select. Drive XTALSEL low to select divider ratio of 64, or drive
XTALSEL high to select divider ratio of 32.
16
14
XTALSEL
17
15
IFIN1
1st Differential Intermediate-Frequency Limiter Amplifier Input. Bypass to AGND with a
1500pF capacitor as close to the pin as possible.
18
16
IFIN2
2nd Differential Intermediate-Frequency Limiter Amplifier Input. Connect to the output of a
10.7MHz bandpass filter.
19
20
21
22
23
17
18
19
20
22
DFO
DSN
OPP
DFFB
DSP
Data Filter Output
Negative Data Slicer Input
Noninverting Op-Amp Input for the Sallen-Key Data Filter
Data-Filter Feedback Node. Input for the feedback of the Sallen-Key data filter.
Positive Data Slicer Input
24
23
V
DD5
+5V Supply Voltage. For +5V operation, V
DD5
is the input to an on-chip voltage regulator
whose +3.2V output drives AV
DD
.
Digital Baseband Data Output
Peak-Detector Output
25
26
24
26
DATAOUT
PDOUT
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