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參數(shù)資料
| 型號： | MAX7000AE |
| 廠商： | Altera Corporation |
| 英文描述： | Programmable Logic Device |
| 中文描述： | 可編程邏輯器件 |
| 文件頁數(shù)： | 9/60頁 |
| 文件大?。?/td> | 943K |
| 代理商： | MAX7000AE |
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Altera Corporation
9
MAX 7000A Programmable Logic Device Data Sheet
For registered functions, each macrocell flipflop can be individually
programmed to implement D, T, JK, or SR operation with programmable
clock control. The flipflop can be bypassed for combinatorial operation.
During design entry, the designer specifies the desired flipflop type; the
Altera software then selects the most efficient flipflop operation for each
registered function to optimize resource utilization.
Each programmable register can be clocked in three different modes:
■
Global clock signal. This mode achieves the fastest clock-to-output
performance.
Global clock signal enabled by an active-high clock enable. A clock
enable is generated by a product term. This mode provides an enable
on each flipflop while still achieving the fast clock-to-output
performance of the global clock.
Array clock implemented with a product term. In this mode, the
flipflop can be clocked by signals from buried macrocells or I/O pins.
■
■
Two global clock signals are available in MAX 7000A devices. As shown
in
Figure 1
, these global clock signals can be the true or the complement of
either of the global clock pins,
GCLK1
or
GCLK2
.
Each register also supports asynchronous preset and clear functions. As
shown in
Figure 2
, the product-term select matrix allocates product terms
to control these operations. Although the product-term-driven preset and
clear from the register are active high, active-low control can be obtained
by inverting the signal within the logic array. In addition, each register
clear function can be individually driven by the active-low dedicated
global clear pin (
GCLRn
). Upon power-up, each register in a MAX 7000AE
device may be set to either a high or low state. This power-up state is
specified at design entry. Upon power-up, each register in EPM7128A and
EPM7256A devices are set to a low state.
All MAX 7000A I/O pins have a fast input path to a macrocell register.
This dedicated path allows a signal to bypass the PIA and combinatorial
logic and be clocked to an input D flipflop with an extremely fast (as low
as 2.5 ns) input setup time.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MAX7000B | Programmable Logic Device |
| MAX7000 | Programmable Logic Device Family |
| MAX7000S | Programmable Logic Device Family |
| MAX7030 | RES 22.1-OHM 1% 0.1W 100PPM THICK-FILM SMD-0603 5K/REEL-7IN-PA |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX7000B | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Programmable Logic Device |
| MAX7000S | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Programmable Logic Device Family |
| MAX700C/D | 功能描述:監(jiān)控電路 RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| MAX700C/D DIE | 制造商:Maxim Integrated Products 功能描述: |
| MAX700CPA | 功能描述:監(jiān)控電路 Integrated Circuits (ICs) RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
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