參數(shù)資料
型號: MAX6958AAEE
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 顯示驅(qū)動器
英文描述: GT 19C 19#16 SKT RECP
中文描述: LED DISPLAY DRIVER, PDSO16
封裝: 0.150 INCH, EXPOSED PAD, QSOP-16
文件頁數(shù): 3/19頁
文件大?。?/td> 270K
代理商: MAX6958AAEE
M
2-Wire Interfaced, 3V to 5.5V, 4-Digit,
9-Segment LED Display Drivers with Keyscan
_______________________________________________________________________________________
3
Note 1:
All parameters tested at T
A
=+25
°
C. Specifications over temperature are guaranteed by design.
Note 2:
Guaranteed by design.
Note 3:
A master device must provide a hold time of at least 300ns for the SDA signal (referred to V
IL
of the SCL signal) in order to
bridge the undefined region of SCL
s falling edge.
Note 4:
C
B
= total capacitance of one bus line in pF. t
R
and t
F
measured between 0.3V+ and 0.7V+.
Note 5:
I
SINK
6mA. C
B
= total capacitance of one bus line in pF. t
R
and t
F
measured between 0.3V+ and 0.7V+.
Note 6:
Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
DC ELECTRICAL CHARACTERISTICS (continued)
(V+ = 3V to 5.5V, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at V+ = 5V, T
A
= +25
°
C.) (Note 1)
PARAMETER
SYMBOL
I
PULLUP
CONDITIONS
MIN
TYP
26.5
MAX
UNITS
μA
Pullup to V+ INPUT1, INPUT2
I
SINK
= 6mA, T
A
= -40
°
C to +85
°
C
I
SINK
= 4mA, T
A
= T
MIN
to T
MAX
I
SINK
= 6mA
0.4
0.4
0.4
IRQ/SEG9, SDA Output Low
Voltage
V
OLBK
V
SDA Output Low Voltage
V
OL(SDA)
V
TIMING CHARACTERISTICS
(V+ = 3V to 5.5V, T
A
= T
MIN
to T
MAX
, Figure 1, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
f
SCL
CONDITIONS
MIN
TYP
MAX
400
UNITS
kHz
Serial Clock Frequency
Bus Free Time Between a STOP
and a START Condition
t
BUF
1.3
μs
Hold Time (Repeated) START
Condition
t
HD, STA
0.6
μs
Repeated START Setup Time
STOP Condition Setup Time
Data Hold Time
Data Setup Time
SCL Clock Low Period
SCL Clock High Period
t
SU, STA
t
SU, STO
t
HD, DAT
t
SU, DAT
t
LOW
t
HIGH
0.6
0.6
μs
μs
μs
ns
μs
μs
(Note 3)
0.9
100
1.3
0.6
Rise Time of Both SDA and SCL
Signals, Receiving
t
R
(Notes 2, 4)
20 +
0.1C
B
300
ns
Fall Time of Both SDA and SCL
Signals, Receiving
t
F
(Notes 2, 4)
20 +
0.1C
B
300
ns
Fall Time of SDA Transmitting
t
F
(Notes 2, 5)
20 +
0.1C
B
50
250
ns
Pulse Width of Spike Suppressed
t
SP
(Note 6)
ns
Capacitive Load for Each Bus
Line
C
B
400
pF
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