參數(shù)資料
型號: MAX6902ETA+T
廠商: Maxim Integrated Products
文件頁數(shù): 5/20頁
文件大?。?/td> 0K
描述: IC RTC SPI COMPAT 8-TDFN
標(biāo)準(zhǔn)包裝: 1
類型: 時鐘/日歷
特點: 警報器,閏年,NVSRAM,Y2K
存儲容量: 31B
時間格式: HH:MM:SS(12/24 小時)
數(shù)據(jù)格式: YY-MM-DD-dd
接口: SPI
電源電壓: 2 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-WDFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 8-TDFN-EP(3x3)
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: MAX6902ETA+TDKR
MAX6902
SPI-Compatible RTC in a TDFN
______________________________________________________________________________________
13
Chip Select
CS serves two functions. First, CS turns on the control
logic that allows access to the Shift register for
Address/Command and data transfer. Second, CS pro-
vides a method of terminating either single-byte or mul-
tiple-byte data transfers. All data transfers are initiated
by driving CS low. If CS is high, then DOUT is high
impedance.
Serial Clock
A clock cycle on SCLK is a rising edge followed by a
falling edge. For data input, data must be valid at DIN
before the rising edge of the clock. For data outputs, bits
are valid on DOUT after the falling edge of the clock.
Data Input (Single-Byte Write)
Following the eight SCLK cycles that input a Single-Byte
Write Address/Command, data bits are input on the ris-
ing edges of the next eight SCLK cycles. Additional
SCLK cycles are ignored. Input data MSB first.
Data Input (Burst Write)
Following the eight SCLK cycles that input a Burst-Write
Address/Command, data bits are input on the rising
edges of the following SCLK cycles. The number of
clock cycles depends on whether the timekeeping reg-
isters or RAM are being written. A Clock Burst Write
requires 1 Address/Command byte, 7 timekeeping data
bytes, and 1 Control register byte. A Burst Write to RAM
may be terminated after any complete data byte by dri-
ving CS high. Input data MSB first (Figure 3).
Data Output (Single-Byte Read
and Burst Read)
A read from the MAX6902 is initiated by an
Address/Command Write from the microcontroller (mas-
ter) to the MAX6902 (slave). The Address/Command
Write portion of the data transfer is clocked into the
MAX6902 on rising clock edges. Following the eighth
falling clock edge of SCLK, after tDO (Figure 4) data
begins to be output on DOUT of the MAX6902. Data
bytes are output MSB first. Additional SCLK cycles
transmit additional data bits, as long as CS remains low.
This permits continuous burst-mode read capability.
Applications Information
Crystal Selection
The MAX6902 is designed to use a standard
32.768kHz watch crystal. Table 1 details the recom-
mended crystal requirements. Some suggested crys-
tals are listed in Table 3. In addition to the specified
SMT devices, some of the listed manufacturers also
offer other package options.
Frequency Stability and Temperature
Timekeeping accuracy of the MAX6902 is dependent
on the frequency stability, of the external crystal. To
determine frequency stability, use the parabolic curve
in Figure 6 and the following equations:
where:
Δf = change in frequency from +25°C (Hz)
f = nominal crystal frequency (Hz)
Δffk
= (T - T)
0
2
CS
SCLK
tDS
DIN
DOUT
tCSS
tCL
tDH
tCH
tCP
tCSH
tCSW
tCSZ
D7
D6
D5
D0
tDO
D7
D0
Figure 5. SPI Bus Timing Diagrams
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