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參數(shù)資料
| 型號： | MAX6892 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Pin-Selectable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors |
| 中文描述： | 引腳可設(shè)置八/六/四路電源排序器/監(jiān)控器 |
| 文件頁數(shù)： | 15/19頁 |
| 文件大?。?/td> | 298K |
| 代理商： | MAX6892 |
M
Pin-Selectable, Octal/Hex/Quad, Power-Supply
Sequencers/Supervisors
______________________________________________________________________________________
15
Manual Reset (
MR
)
Many μP-based products require manual reset capabil-
ity to allow an operator or external logic circuitry to initi-
ate a reset. The manual reset input (
MR
) can connect
directly to a switch without an external pullup resistor or
debouncing network.
MR
is internally pulled up to DBP
through a 10μA current source and, therefore, can be
left unconnected if unused.
MR
is designed to reject fast falling transients (typically
100ns pulses) and it must be held low for a minimum of
1μs to assert
RESET
. After
MR
transitions from low to
high,
RESET
remains asserted for the duration of the
reset timeout period.
Margin Output Disable (
MARGIN
)
MARGIN
allows system-level testing while power sup-
plies exceed the normal ranges. Driving
MARGIN
low
forces PG_,
RESET
, and
WDO
to hold the last state
while system-level testing occurs. Leave
MARGIN
unconnected or connect to DBP if unused. An internal
10μA current source pulls
MARGIN
to DBP. The state of
each programmable output,
RESET
, and
WDO
does
not change while
MARGIN
= GND.
Enable Input
ENABLE
is an active-high, logic input. Driving
ENABLE
high pulls all PG_ low. Drive
ENABLE
high or leave
floating for normal operation.
ENABLE
is internally
pulled down to GND through a 10μA current sink.
Power-Good Outputs
The MAX6892 features eight power-good outputs, the
MAX6893 features six power-good outputs, and the
MAX6894 features four power-good outputs. Each out-
put (PG_) responds to its respective input (IN_). Each
PG_ is open drain. During power-up, the outputs pull
down to GND with an internal 10μA current sink for 1V
< V
CC
< V
UVLO
.
RESET
Output
The reset output is typically connected to the reset
input of a μP. A μP’s reset input starts or restarts the μP
in a known state. The MAX6892/MAX6893/MAX6894
supervisory circuits provide the reset logic to prevent
code-execution errors during power-up, power-down,
and brownout conditions.
RESET
changes from high to low whenever one or more
input voltage (IN1–IN8) monitors drop below their
respective reset threshold voltage or when
MR
is pulled
low for a minimum of 1μs. Once the affected input volt-
age monitor(s) exceeds its respective reset threshold
voltage(s),
RESET
remains low for the reset timeout
period, then deaaserts.
Applications Information
Selecting the Reset/Watchdog
Timeout Capacitor
The reset timeout period can be adjusted to accommo-
date a variety of μP applications. Adjust the reset time-
out period (t
RP
) by connecting a capacitor (C
SRT
)
between SRT and ground. Calculate the reset timeout
capacitor as follows:
C
SRT
= t
RP
/ (4.348 x 106)
with t
RP
in seconds and C
SRT
in Farads. Connect SRT
to V
CC
for a factory-programmed reset timeout of
200ms (typ).
The watchdog timeout period can be adjusted to
accommodate a variety of μP applications. With this
feature, the watchdog timeout can be optimized for
software execution. The programmer can determine
how often the watchdog timer should be serviced.
Adjust the watchdog timeout period (t
WD
) by connect-
ing a specific value capacitor (C
SWT
) between SWT
and GND. For normal mode operation, calculate the
watchdog timeout capacitor as follows:
C
SWT
= t
WD
/ (4.348 x 10
6
)
with t
WD
in seconds and C
SWT
in Farads. Connect SWT
to V
CC
for a factory-programmed watchdog timeout of
1.6s (normal mode) and 102.4s (initial mode).
C
SRT
and C
SWT
must be a low-leakage (<10nA) type
capacitor. Ceramic capacitors are recommended.
Layout and Bypassing
For better noise immunity, bypass each of the voltage
detector inputs to GND with 0.1μF capacitors installed
as close to the device as possible. Bypass V
CC
and
DBP to GND with 1μF capacitors installed as close to
the device as possible.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX6892ETJ | 功能描述:監(jiān)控電路 RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| MAX6892ETJ+ | 功能描述:監(jiān)控電路 Pin-Selectable Octal Power-Sup Sequencer RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| MAX6892ETJ+T | 功能描述:監(jiān)控電路 Pin-Selectable Octal Power-Sup Sequencer RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| MAX6892ETJ-T | 功能描述:監(jiān)控電路 RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| MAX6893ETI | 功能描述:監(jiān)控電路 RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
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