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參數(shù)資料
| 型號(hào)： | MAX6878ETG* |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Dual-/Triple-Voltage, Power-Supply Trackers/Sequencers/Supervisors |
| 中文描述： | Dual-/Triple-Voltage，電源追蹤器/排序器/監(jiān)控 |
| 文件頁數(shù)： | 17/24頁 |
| 文件大小： | 307K |
M
Dual-/Triple-Voltage, Power-Supply
Trackers/Sequencers/Supervisors
______________________________________________________________________________________
17
During ramp up, if an OUT_ voltage is less than the ref-
erence ramp voltage by more than 125mV, the control
loop dynamically stops the control ramp voltage from
rising until the slow OUT_ voltage catches up. If an
OUT_ voltage is greater or less than the reference ramp
voltage by more than 250mV, a fault is signaled and a
power-down phase is initiated.
The slew rate for the reference ramp voltage is capaci-
tor adjustable. Connect a capacitor from SLEW to
ground to select the desired OUT_ slew rate. When all
OUT_ voltages have exceeded the V
TH_PG
percentage
of the IN_ voltage (external n-channel FET is saturated),
PG/
RST
asserts high after t
TIMEOUT
indicating success-
ful tracking.
Sequencing
The sequencing operation can be initiated after all
input conditions for power-up are met V
EN/
UV
> 1.25V
and all SET_ inputs are above the internal SET_ thresh-
old (0.5V). In sequencing mode, the outputs are turned
on sequentially, OUT1 first and OUT3 last. Before turn-
ing on each channel, a delay period occurs as in
Figure 3 (programmable by connecting a capacitor
from DELAY to ground). The power-up phase for each
channel ends when its output voltage exceeds a fixed
percentage (V
TH_PG
) of the corresponding IN_ voltage.
When all channels have exceeded these thresholds,
PG/
RST
asserts high after t
TIMEOUT
, indicating a suc-
cessful sequence.
If there is a fault condition during the initial power-up
sequence, the process is aborted.
When powering down, all outputs turn off simultaneous-
ly, tracking each other. No reverse power-down
sequencing occurs.
Power-Up and Power-Down
During power-up, the OUT_ is forced to follow the internal
reference ramp voltage by an internal loop that controls
the GATE_ of the external MOSFET. This phase must be
completed within the adjustable fault timeout period; oth-
erwise, the part forces a shutdown on all GATE_.
Once the power-up is completed, a power-down phase
can be initiated by forcing V
EN/
UV
below V
EN_F
. The
reference voltage ramp ramps down at the capacitor-
adjusted slew rate. The control-loop comparators moni-
tor each OUT_ voltage with respect to the common
reference ramp voltage. During ramp down, if an OUT_
voltage is greater than the reference ramp voltage by
more than V
TRK
, the control loop dynamically stops the
control ramp voltage from decreasing until the slow
OUT_ voltage catches up. If an OUT_ voltage is greater
or less than the reference ramp voltage by more than
V
TRK_F
, a fault is signaled and the fast-shutdown mode
is initiated. In fast-shutdown mode, a 100
pulldown
resistor is connected from OUT_ to GND to quickly dis-
charge capacitance at OUT_ and GATE _ is pulled low
with a strong I
GDS
current (see Figures 2 and 4).
Figures 5 and 6 show aborted tracking and sequencing
modes. When EN/
UV
goes low before t
TIMEOUT
expires, all the outputs go low and the device goes into
fast shutdown.
Internal Pulldown
To ensure that the OUT_ voltages are not held high by
a large output capacitance after a fault has occurred,
there is a 100
internal pulldown at OUT_. The pull-
down ensures that all OUT_ voltages are below V
TH_PL
(referenced to GND) before power-up cycling is initiat-
ed. The internal pulldown also ensures a fast discharge
of the output capacitor during fast shutdown and fault
modes. The pulldowns are not present during normal
operation.
Stability Comment
No external compensation is required for tracking or
slew-rate control.
Inputs
IN1/IN2/IN3
The highest voltage on V
CC
, IN1, IN2, or IN3 supplies
power to the device. The undervoltage threshold for
each IN_ supply is set with an external resistor-divider
from each IN_ to SET_ to ground.
Undervoltage Lockout Threshold Inputs (SET_)
The MAX6877 features three and the MAX6878/
MAX6879 feature two externally adjustable IN_ under-
voltage lockout (UVLO) thresholds (SET1, SET2, SET3) to
enable sequencing/tracking functionality. The undervolt-
age threshold for each IN_ supply is set with an exter-
nal resistor-divider from each IN_ to SET_ to ground
(see Figure 9). All SET_ inputs must be above the inter-
nal SET_ threshold (0.5V) to enable tracking/sequenc-
ing functionality. Use the following formula to set the
UVLO threshold:
V
IN_
= V
TH
(R1 + R2) / R2
where V
IN_
is the undervoltage lockout threshold and
V
TH
is the 500mV SET threshold.
Margin Input (
MARGIN
)
MARGIN
allows system-level testing while power sup-
plies are below the normal ranges as adjusted by the
SET_ inputs. Drive
MARGIN
low before varying system
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX6878ETG+ | 功能描述:監(jiān)控電路 Dual Power-Sup Sequencer RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| MAX6878ETG+T | 功能描述:監(jiān)控電路 Dual Power-Sup Sequencer RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| MAX6878ETG-T | 功能描述:監(jiān)控電路 RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| MAX6879ETE | 功能描述:監(jiān)控電路 RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| MAX6879ETE+ | 功能描述:監(jiān)控電路 Dual Power-Sup Sequencer RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
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