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參數(shù)資料
| 型號： | MAX6852AEE |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 顯示驅(qū)動器 |
| 英文描述： | 4-Wire Interfaced, 5 x 7 Matrix Vacuum- Fluorescent Display Controller |
| 中文描述： | VACUUM FLUOR DISPLAY DRIVER, PDSO16 |
| 封裝： | 0.150 INCH, 0.025 INCH PITCH, MO-137AA, QSOP-16 |
| 文件頁數(shù)： | 15/32頁 |
| 文件大小： | 489K |
| 代理商： | MAX6852AEE |
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M
4-Wire Interfaced, 5
7 Matrix Vacuum-
Fluorescent Display Controller
______________________________________________________________________________________
15
ister, high-voltage grid/anode VFD tube drivers (Figures
3 and 4). The speed of VFCLK is 2MHz when OSC is
4MHz. The maximum speed of VFCLK is 4MHz when
OSC is 8MHz. This interface is used to transfer display
data from the MAX6852 to the VFD tube driver. The ser-
ial interface bit stream output is programmable up to
122 bits, which are labeled DD0
–
DD121.
The functions of the three interface pins are as follows:
VFCLK is the serial clock output, which shifts data on
its falling edge from the MAX6852
’
s 122-bit output shift
register to VFLOAD.
VFDOUT is the serial data output. The data changes on
VFCLK
’
s falling edge, and is stable when it is sampled
by the display driver on the rising edge of VFCLK.
VFLOAD is the latch-load output. VFLOAD is high to
transfer data from the display tube driver
’
s shift register to
the display driver
’
s output latch (transparent mode), and
low to retain that data in the display driver
’
s output latch.
A fourth output pin, VFBLANK, provides gating control
of the tube driver. VFBLANK can be configured to be
either high or low using the VBLANK polarity register
(Table 26) to enable the VFD tube driver. In the default
condition, VFBLANK is high to disable the VFD tube dri-
ver, which is expected to force its driver outputs low to
blank the display without altering the contents of its out-
put latches. In the default condition, VFBLANK is low to
enable its VFD tube driver outputs to follow the state of
the VFD tube driver
’
s output latches. The VFBLANK
output is used for PWM intensity control and to disable
the VFD tube driver in shutdown.
Multiplex Architecture
The multiplex engine transmits grid and anode control
data to the external VFD driver using the VFCLK, VFD-
OUT, and VFLOAD. The number of data bits m trans-
mitted is set by the user in the shift-limit register (Table
28). Figure 10 is the VFD multiplex timing diagram.
The essential rules for multiplex action are as follows:
The external VFD driver
’
s data latch contains the
data for the current grid being displayed.
The VFBLANK input is controlled to provide the
PWM intensity control.
The VFCLK and VFDOUT outputs are used to fill the
external VFD driver
’
s shift register with the multiplex
data for the next grid, during the multiplex timeslot
for the current grid.
The VFLOAD output loads the new grid-anode data
pattern at the start of its multiplex cycle.
Grids Register
The grids register sets how many grids are multiplexed
from 1 to 48 (Table 24).
When the grids register is written, the external VFD tube
driver is presumed to contain invalid data. The
VFBLANK output is used to disable the VFD tube driver
for the first multiplex cycle after exiting shutdown, clear-
ing any invalid data. The next multiplex cycle uses
newly sent, valid data. If the grids register is written
with an out-of-range value of 0x30 to 0xFF, then the
value 0x2F is stored instead.
Intensity Register
Digital control of display brightness is provided by
pulse-width modulation of the tube blanking time, which
is controlled by the lower nibble of the intensity register
(Table 25). The modulator scales the VFBLANK output
in 15 steps from a minimum of 1/16 up to 15/16 of each
grid
’
s multiplex period (Figure 11). Figure 12 shows the
modulator behavior when the VFBLANK polarity regis-
ter is set to 0x00 (Table 26), so VFBLANK is high to dis-
able (blank) the display.
The minimum off-time period of a 1/16 multiplex period
(6.25μs with OSC = 4MHz) is always at the start of the
multiplex cycle. This allows time for slow display drivers
to turn off, and slow display phosphors time to decay
CS
CLK
DIN
BIT
1
BIT
2
N-9
N-8
N-7
N-6
N-5
N-4
N-3
N-2
DOUT
N-15 = 0
N-15
= 0
N-14
N-13
N-12
N-11
N-10
N-1
N-31
N-30
N-29
N-28
N-27
N-26
N-25
N-24
N-23
N-22
N-21
N-20
N-19
N-18
N-17
N-16
N
Figure 8. Transmission of More than 16 Bits to the MAX6852
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX6852AEE+ | 功能描述:VFD驅(qū)動器 Integrated Circuits (ICs) PMIC - Display Drivers - IC VFD CTRLR MATRIX 16QSOP RoHS:否 制造商:Maxim Integrated 工作電源電壓:8 V to 76 V, 3 V to 5.5 V 電源電流:0.9 mA, 700 uA 最大工作溫度:+ 125 C 封裝 / 箱體:SOIC-20 封裝:Tube |
| MAX6852AEE+T | 功能描述:VFD驅(qū)動器 Integrated Circuits (ICs) PMIC - Display Drivers - IC VFD CTRLR MATRIX 16QSOP RoHS:否 制造商:Maxim Integrated 工作電源電壓:8 V to 76 V, 3 V to 5.5 V 電源電流:0.9 mA, 700 uA 最大工作溫度:+ 125 C 封裝 / 箱體:SOIC-20 封裝:Tube |
| MAX6852AEE-T | 功能描述:VFD驅(qū)動器 RoHS:否 制造商:Maxim Integrated 工作電源電壓:8 V to 76 V, 3 V to 5.5 V 電源電流:0.9 mA, 700 uA 最大工作溫度:+ 125 C 封裝 / 箱體:SOIC-20 封裝:Tube |
| MAX6853AEE | 功能描述:VFD驅(qū)動器 RoHS:否 制造商:Maxim Integrated 工作電源電壓:8 V to 76 V, 3 V to 5.5 V 電源電流:0.9 mA, 700 uA 最大工作溫度:+ 125 C 封裝 / 箱體:SOIC-20 封裝:Tube |
| MAX6853AEE+T | 功能描述:VFD驅(qū)動器 RoHS:否 制造商:Maxim Integrated 工作電源電壓:8 V to 76 V, 3 V to 5.5 V 電源電流:0.9 mA, 700 uA 最大工作溫度:+ 125 C 封裝 / 箱體:SOIC-20 封裝:Tube |
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