參數(shù)資料
型號(hào): MAX6652AUB+T
廠商: Maxim Integrated
文件頁(yè)數(shù): 8/12頁(yè)
文件大?。?/td> 165K
描述: IC TEMP SENS/MON 10-UMAX
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
功能: 溫度監(jiān)控系統(tǒng)(傳感器)
傳感器類(lèi)型: 內(nèi)部
感應(yīng)溫度: -40°C ~ 125°C
精確度: ±2°C(最小值)
拓?fù)洌?/td> ADC,多路復(fù)用器,寄存器庫(kù)
輸出類(lèi)型: I²C?/SMBus?
輸出警報(bào):
輸出風(fēng)扇: 無(wú)
電源電壓: 2.7 V ~ 5.5 V
工作溫度: -40°C ~ 125°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-uMAX
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁(yè)面: 1425 (CN2011-ZH PDF)
其它名稱(chēng): MAX6652AUB+TDKR
Low-Power Shutdown Mode
Setting bit 0 in the configuration register to 0 stops the
monitoring loop and puts the MAX6652 into low-power
shutdown mode. In this mode, the I
2
C-compatible/
SMBus interface remains active, and the supply current
drops to 10礎(chǔ) or less.
Power-On Reset (POR)
The MAX6652 power-on reset supply (POR) voltage is
typically 2V. Below this supply voltage, all registers are
reset, the device is put into shutdown mode, and the
I
2
C-compatible/SMBus interface is inactive.
Alarm Threshold Registers
Two registers, a hot temperature limit (T
HOT
) at 39h and
a hot temperature hysteresis (T
HYST
) at 3Ah, store
alarm threshold data (Table 1). If a measured tempera-
ture exceeds the value of T
HOT
, an ALERT is asserted.
Alerts are cleared and reasserted depending on the
interrupt mode selected in the temperature configura-
tion register (see ALERT Interrupts).
The POR state of the T
HOT
register is 0101 0000 or
+80癈. The POR state of the T
HYST
register is 0100
0001 or +65癈.
High and low limits for the voltage inputs are stored in
registers 2Bh through 32h. If a measured voltage is
less than V
LOW
or greater than V
HIGH
, an ALERT is
asserted.
The POR states of the high- and low-voltage limits are
1.1 and 0.9 times the nominal voltage for each input,
respectively.
Interrupt Status Byte Functions
The interrupt status register records temperature or
voltage fault conditions whenever a limit is exceeded
(Table 5). Bits 0 through 3 correspond to the 2.5V, 12V,
3.3V, and 5V internal V
CC
voltage inputs, and bit 4 cor-
responds to the temperature. If a threshold has been
crossed, the appropriate bit will contain a 1. In the
default and one-time interrupt modes, reading the sta-
tus register clears the register until a new out-of-range
condition is detected.
ALERT Interrupts
An out-of-range voltage or temperature causes the
ALERT output signal to be asserted. However, if the
assertion is caused by an out-of-range temperature, the
ALERT output can operate in one of three different
modes: default, one-time interrupt, and comparator
modes. The ALERT signal can be cleared only by read-
ing the interrupt status register (Table 5), except when
the ALERT has been activated by an out-of-range tem-
perature in comparator mode. In this case, ALERT is
only cleared when the fault is removed. Reading the
interrupt status register also clears this register, except
for bit 4 in comparator mode. Unless the fault is
removed, ALERT will be reasserted after the next con-
version cycle. The ALERT output can also be masked
by writing to the appropriate bits in the interrupt mask
register (Table 6) or by setting bit 1 of the configuration
register (Table 4) to 0.
The interrupt does not halt conversions. New tempera-
ture and voltage data continue to be available over the
I
2
C-compatible/SMBus interface after ALERT is assert-
ed. The three temperature ALERT modes are illustrated
in Figure 1 and are selected through the temperature
configuration register (Table 7). The ALERT output pin
is open drain, so the device can share a common inter-
rupt line.
Temperature Sensor and System Monitor
in a 10-Pin 礛AX
8  _______________________________________________________________________________________
Table 6. Interrupt Mask Register (Address 43h, Power-Up Default = 00h)
BIT
NAME
READ/WRITE
DESCRIPTION
0
2.5V
R/W
Setting the bit to 1 disables the interrupt status register bit (bit 0) and the ALERT
output for the 2.5V
IN
 input.
1
12V
R/W
Setting the bit to 1 disables the interrupt status register bit (bit 1) and the ALERT
output for the 12V
IN
 input.
2
3.3V
R/W
Setting the bit to 1 disables the interrupt status register bit (bit 2) and the ALERT
output for the 3.3V
IN
 input.
3
5.0V
R/W
Setting the bit to 1 disables the interrupt status register bit (bit 3) and the ALERT
output for the V
CC
 input.
4
Tem p er atur e
R/W
Setting the bit to 1 disables the interrupt status register bit (bit 4) and the ALERT
output for temperature.
5, 6, 7
Reserved


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