參數(shù)資料
型號(hào): MAX6421US__-T
廠商: Maxim Integrated Products, Inc.
英文描述: Low-Power, SC70/SOT レP Reset Circuits with Capacitor-Adjustable Reset Timeout Delay
中文描述: 低功耗,SC70/SOTレP復(fù)位電路,帶有電容可調(diào)的復(fù)位延遲時(shí)間
文件頁(yè)數(shù): 5/10頁(yè)
文件大?。?/td> 263K
代理商: MAX6421US__-T
M
Low-Power, SC70/SOT μP Reset Circuits with
Capacitor-Adjustable Reset Timeout Delay
_______________________________________________________________________________________
5
C
SRT
= (t
RP
- 275μs) / (2.73
10
6
)
where t
RP
is in seconds and C
SRT
is in farads.
The reset delay time is set by a current/capacitor-con-
trolled ramp compared to an internal 0.65V reference.
An internal 240nA ramp current source charges the
external capacitor. The charge to the capacitor is
cleared when a reset condition is detected. Once the
reset condition is removed, the voltage on the capacitor
ramps according to the formula: dV/dt = I/C. The C
SRT
capacitor must ramp to 0.65V to deassert the reset.
C
SRT
must be a low-leakage (<10nA) type capacitor;
ceramic is recommended.
Operating as a Voltage Detector
The MAX6340/MAX6421–MAX6426 can be operated in a
voltage detector mode by floating the SRT pin. The reset
delay times for V
CC
rising above or falling below the
threshold are not significantly different. The reset output is
deasserted smoothly without false pulses.
Applications Information
Interfacing to Other Voltages for Logic
Compatibility
The open-drain outputs of the MAX6340/MAX6423/
MAX6425/MAX6426 can be used to interface to μPs with
other logic levels. As shown in Figure 1, the open-drain
output can be connected to voltages from 0 to 5.5V. This
allows for easy logic compatibility to various μPs.
Wired-OR Reset
To allow auxiliary circuitry to hold the system in reset,
an external open-drain logic signal can be connected
to the open-drain
RESET
of the MAX6340/MAX6423/
MAX6425/MAX6426, as shown in Figure 2. This config-
uration can reset the μP, but does not provide the reset
timeout when the external logic signal is released.
Negative-Going V
CC
Transients
In addition to issuing a reset to the μP during power-up,
power-down, and brownout conditions, these supervisors
are relatively immune to short-duration negative-going
transients (glitches). The graph Maximum Transient
Duration vs. Reset Threshold Overdrive in the
Typical
Operating Characteristics
shows this relationship.
The area below the curve of the graph is the region in
which these devices typically do not generate a reset
pulse. This graph was generated using a negative-
going pulse applied to V
CC
, starting above the actual
reset threshold (V
TH
) and ending below it by the magni-
tude indicated (reset-threshold overdrive). As the mag-
nitude of the transient decreases (farther below the
reset threshold), the maximum allowable pulse width
decreases. Typically, a V
CC
transient that goes 100mV
below the reset threshold and lasts 50μs or less does
not cause a reset pulse to be issued.
Ensuring a Valid RESET or
RESET
Down to V
CC
= 0
When V
CC
falls below 1V,
RESET
/RESET current-sink-
ing (sourcing) capabilities decline drastically. In the
case of the MAX6421/MAX6424, high-impedance
CMOS-logic inputs connected to
RESET
can drift to
undetermined voltages. This presents no problems in
most applications, since most μPs and other circuitry
do not operate with V
CC
below 1V.
In those applications where
RESET
must be valid down
to zero, adding a pulldown resistor between
RESET
and ground sinks any stray leakage currents, holding
RESET
low (Figure 3). The value of the pulldown resis-
tor is not critical; 100k
is large enough not to load
RESET
and small enough to pull
RESET
to ground. For
applications using the MAX6422, a 100k
pullup resis-
V
DD
V
CC
MAX6340
MAX6423
MAX6425
MAX6426
RESET
N
N
GND
OPEN-DRAIN
LOGIC
μ
P
RESET
10k
Figure 2. Wired-OR Reset Circuit
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