![](http://datasheet.mmic.net.cn/390000/MAX6316L_datasheet_16818431/MAX6316L_7.png)
M
5-Pin μP S upervisory Circ uits with
Watc hdog and Manual Reset
_______________________________________________________________________________________
7
Bidirec tional
RESET
Output
The MAX6316M/MAX6318MH/MAX6319MH are designed
to interface with μPs that have bidirectional reset pins,
such as the Motorola 68HC11. Like an open-drain output,
these devices allow the μP or other devices to pull the
bidirectional reset (
RESET
) low and assert a reset condi-
tion. However, unlike a standard open-drain output, it
includes the commonly specified 4.7k
pull-up resistor
with a P-channel active pull-up in parallel.
This configuration allows the MAX6316M/MAX6318MH/
MAX6319MH to solve a problem associated with μPs
that have bidirectional reset pins in systems where sev-
eral devices connect to
RESET
(Figure 3). These μPs
can often determine if a reset was asserted by an exter-
nal device (i.e., the supervisor IC) or by the μP itself
(due to a watchdog fault, clock error, or other source),
and then jump to a vector appropriate for the source of
the reset. However, if the μP does assert reset, it does
not retain the information, but must determine the
cause after the reset has occurred.
The following procedure describes how this is done in
the Motorola 68HC11. In all cases of reset, the μP pulls
RESET
low for about four external-clock cycles. It then
releases
RESET
, waits for two external-clock cycles,
then checks
RESET
’s state. If
RESET
is still low, the μP
concludes that the source of the reset was external
and, when
RESET
eventually reaches the high state, it
jumps to the normal reset vector. In this case, stored-
state information is erased and processing begins from
scratch. If, on the other hand,
RESET
is high after a
delay of two external-clock cycles, the processor
knows that it caused the reset itself and can jump to a
different vector and use stored-state information to
determine what caused the reset.
A problem occurs with faster μPs; two external-clock
cycles are only 500ns at 4MHz. When there are several
devices on the reset line, and only a passive pull-up resis-
tor is used, the input capacitance and stray capacitance
can prevent
RESET
from reaching the logic high state (0.8
x V
CC
) in the time allowed. If this happens, all resets will
be interpreted as external. The μP output stage is guaran-
teed to sink 1.6mA, so the rise time can not be reduced
considerably by decreasing the 4.7k
internal pull-up
resistance. See Bidirectional Pull-Up Characteristics in the
Typical Operating Characteristics.
The MAX6316M/MAX6318MH/MAX6319MH overcome
this problem with an active pull-up FET in parallel with the
4.7k
resistor (Figures 4 and 5). The pull-up transistor
holds
RESET
high until the μP reset I/O or the supervisory
circuit itself forces the line low. Once
RESET
goes below
V
PTH
, a comparator sets the transition edge flip-flop, indi-
cating that the next transition for
RESET
will be low to
high. When
RESET
is released, the 4.7k
resistor pulls
RESET
up toward V
CC
. Once
RESET
rises above V
PTH
but is below (0.85 x V
CC
), the active P-channel pull-up
turns on. Once
RESET
rises above (0.85 x V
CC
) or the
2μs one-shot times out, the active pull-up turns off. The
parallel combination of the 4.7k
pull-up and the
4.7k
MR**
C
IN
RESET
RESET
CIRCUITRY
RESET***
WDI*
V
CC
MAX6316M
MAX6318MH
MAX6319MH
C
STRAY
68HC11
RESET
CIRCUITRY
C
IN
RESET
V
CC
OTHER DEVICES
C
IN
RESET
MAX6316M/MAX6318MH
MAX6316M/MAX6319MH
ACTIVE-HIGH PUSH/PULL MAX6318MH/MAX6319MH
*
**
***
Figure 3. MAX6316M/MAX6318MH/MAX6319MH Supports Additional Devices on the Reset Bus