參數(shù)資料
型號(hào): MAX5945
廠商: Maxim Integrated Products, Inc.
英文描述: Quad Network Power Controller for Power-Over-LAN
中文描述: 四路網(wǎng)絡(luò)電源控制器,用于LAN供電
文件頁(yè)數(shù): 5/44頁(yè)
文件大?。?/td> 572K
代理商: MAX5945
M
Quad Network Power Controller
for Power-Over-LAN
_______________________________________________________________________________________
5
ELECTRICAL CHARACTERISTICS (continued)
(AGND = +32V to +60V, V
EE
= 0V, V
DD
to DGND = +3.3V, all voltages are referenced to V
EE
, unless otherwise noted. Typical
values are at AGND = +48V, DGND = +48V, V
DD
= (DGND + 3.3V), T
A
= +25°C. Currents are positive when entering the pin and
negative otherwise.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Internal Input Pullup/Pulldown
Resistor
R
DIN
Pullup (pulldown) resistor to V
DD
(DGND) to set
default level
25
50
75
k
Open-Drain Output Low
Voltage
V
OL
I
SINK
= 15mA
0.4
V
Open-Drain Leakage
TIMING
I
OL
Open-drain high impedance, V
O
= 3.3V
2
μA
Startup Time
t
START
Time during which a current limit set by V
SU_LIM
is allowed, starts when the GATE_
is turned on (Note 8)
50
60
70
ms
Fault Time
t
FAULT
Maximum allowed time for an overcurrent
condition set by V
FLT_LIM
after startup (Note 8)
50
60
70
ms
Port Turn-Off Time
t
OFF
Minimum delay between any port turning off,
does not apply in the case of a reset
0.5
0.75
1.0
ms
Detection Time
t
DET
Maximum time allowed before detection
is completed
320
ms
Midspan Mode Detection
Delay
Classification Time
t
DMID
2.0
2.4
s
t
CLASS
Time allowed for classification
40
ms
V
EEUVLO
Turn-On Delay
t
DLY
Time V
AGND
must be above the V
EEUVLO
thresholds before the device operates
2
4
ms
RSTR bits = 00
16 x
t
FAULT
RSTR bits = 01
32 x
t
FAULT
RSTR bits = 10
64 x
t
FAULT
0
164
Restart Timer
t
RESTART
Ti m e a p or has to w ai
b efor e tur ni ng on after an
over cur ent faul ,
RS TR_E N b = hi g h
RSTR bits = 11
ms
Watchdog Clock Period
TIMING CHARACTERISTICS for 2-WIRE FAST MODE
(Figures 5 and 6)
Serial Clock Frequency
f
SCL
Bus Free Time Between a
STOP and a START Condition
t
WD
Rate of decrement of the watchdog timer
ms
(Note 9)
400
kHz
t
BUF
(Note 9)
1.2
μs
Hold Time for Start Condition
Low Period of the SCL Clock
High Period of the SCL Clock
t
HD, STA
t
LOW
t
HIGH
(Note 9)
(Note 9)
(Note 9)
0.6
1.2
0.6
μs
μs
μs
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