參數(shù)資料
型號: MAX5937LCESA+
廠商: Maxim Integrated
文件頁數(shù): 17/23頁
文件大?。?/td> 382K
描述: IC HOT-SWAP CTRLR -48V 8-SOIC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 100
類型: 熱交換控制器
應(yīng)用: 通用
內(nèi)部開關(guān):
電源電壓: -10 V ~ -80 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOIC
包裝: 管件
-48V Hot-Swap Controllers with V
IN
Step Immunity and No R
SENSE
______________________________________________________________________________________   17
load-probe, and V
EE
. Because of the nature of the hot-
swap requirement, no decoupling capacitor is recom-
mended for the MAX5936/MAX5937. Because there is
no decoupling capacitor, stray inductance can result in
excessive ringing at the GND pin during power-up or
during very rapid V
IN
steps. This should be examined
in every application design since ringing at the GND
pin may exceed the absolute maximum supply rating
for the part.
Input Transient Protection
During hot plug-in/unplug and fast V
IN
steps, stray
inductance in the power path can cause voltage ring-
ing above the normal input DC value, which may
exceed the absolute maximum supply rating. An input
transient such as that caused by lightning can also put
a severe transient peak voltage on the input rail. The
following techniques are recommended to reduce the
effect of transients:
1)  Minimize stray inductance in the power path using
wide traces and minimize loop area including the
power traces and the return ground path.
2)  Add a high-frequency (ceramic) bypass capacitor
on the backplane as close as possible to the plug-
in connector (Figure 17).
3)  Add a 1k& resistor in series with the MAX5936/
MAX5937s GND pin and a 0.1礔 capacitor from
GNDtoV
EE
to limit transientcurrent going into this pin.
Appendix A
GATE Cycles
The power-up GATE cycle and the step GATE cycle are
quite similar but have distinct differences. Understanding
these differences may clarify application issues.
GATE Cycle During Power-Up
The power-up GATE cycle occurs during the initial
power-up of the MAX5936/MAX5937 and the associat-
ed power MOSFET and load. The power-up GATE
cycle can result in full enhancement or in a fault (all
voltages are relative to V
EE
).
Power-Up to Full Enhancement:
1)  At the beginning of the power-up sequence to the
start of the power-up GATE cycle, the GATE is held
at V
EE
. Following a successful completion of the
load-probe test, GATE is held at V
EE
for an addi-
tional 350祍 and then is allowed to float for 650祍.
At this point, the GATE begins to ramp with 52礎(chǔ)
charging the gate of the power MOSFET. [GATE
turn-on]
2)  When GATE reaches the gate threshold voltage of
the power MOSFET, V
OUT
begins to ramp down
toward V
EE
. [V
OUT
ramp]
3)  When V
OUT
ramps below 72% V
CB
, the GATE is
rapidly pulled to full enhancement and the power-
up GATE cycle is complete. 1.26ms after GATE is
pulled to full enhancement, PGOOD will assert. [Full
enhancement]
Figure 15. MAX5936/MAX5937 Slew Rate vs. C
SLEW
SLEW RATE vs. C
SLEW
C
SLEW
 (nF)
100
10
1
0.1
1
10
0.01
0.1
1000
Figure 16. Adjusting the MAX5936/MAX5937 Slew Rate
MAX5936
MAX5937
V
OUT
C
LOAD
LOAD
GATE
V
EE
GND
C
SLEW
R
GATE
-48V
GND
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MAX5937LCESA-T 功能描述:熱插拔功率分布 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Controllers & Switches 電流限制: 電源電壓-最大:7 V 電源電壓-最小:- 0.3 V 工作溫度范圍: 功率耗散: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Tube
MAX5937LNESA 功能描述:熱插拔功率分布 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Controllers & Switches 電流限制: 電源電壓-最大:7 V 電源電壓-最小:- 0.3 V 工作溫度范圍: 功率耗散: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Tube
MAX5937LNESA+ 功能描述:熱插拔功率分布 48V- Hot-Swap Controller RoHS:否 制造商:Texas Instruments 產(chǎn)品:Controllers & Switches 電流限制: 電源電壓-最大:7 V 電源電壓-最小:- 0.3 V 工作溫度范圍: 功率耗散: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Tube