參數資料
型號: MAX5894EGK+D
廠商: Maxim Integrated Products
文件頁數: 29/32頁
文件大?。?/td> 0K
描述: IC DAC 14BIT DUAL 500MSPS 68-QFN
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 30
設置時間: 11ns
位數: 14
數據接口: 并聯
轉換器數目: 2
電壓電源: 模擬和數字
功率耗散(最大): 886mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 68-VFQFN 裸露焊盤
供應商設備封裝: 68-QFN 裸露焊盤(10x10)
包裝: 管件
輸出數目和類型: 2 電流,單極
采樣率(每秒): 500M
MAX5894
14-Bit, 500Msps, Interpolating and Modulating
Dual DAC with CMOS Inputs
6
_______________________________________________________________________________________
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLIES
Digital Supply Voltage
DVDD1.8
1.71
1.8
1.89
V
Digital I/O Supply Voltage
DVDD3.3
3.0
3.3
3.6
V
Clock Supply Voltage
AVCLK
3.135
3.3
3.465
V
AVDD3.3
3.135
3.3
3.465
Analog Supply Voltage
AVDD1.8
1.71
1.8
1.89
V
IAVDD3.3
fCLK = 250MHz, 2x interpolation, 0dBFS,
fOUT = 10MHz
110
130
Analog Supply Current
IAVDD1.8
fCLK = 250MHz, 2x interpolation, 0dBFS,
fOUT = 10MHz
27
32
mA
Digital Supply Current
IDVDD1.8
fCLK = 250MHz, 2x interpolation, 0dBFS,
fOUT = 10MHz
225
250
mA
Digital I/O Supply Current
IDVDD3.3
fCLK = 250MHz, 2x interpolation, 0dBFS,
fOUT = 10MHz
21
32
mA
Clock Supply Current
IAVCLK
fCLK = 250MHz, 2x interpolation, 0dBFS,
fOUT = 10MHz
35
mA
Total Power Dissipation
PTOTAL
fCLK = 250MHz, 2x interpolation, 0dBFS,
fOUT = 10MHz
886
mW
AVDD3.3
450
AVDD1.8
1
DVDD1.8
10
DVDD3.3
100
Power-Down Current
All I/O are static high or
low, bit 2 to bit 4 of
address 00h are set high
AVCLK
1
A
AVDD3.3 Power-Supply Rejection
Ratio
PSRRA
(Note 9)
0.05
%FS/V
ELECTRICAL CHARACTERISTICS (continued)
(DVDD1.8 = AVDD1.8 = 1.8V, AVCLK = AVDD3.3 = DVDD3.3 = 3.3V, modulator off, 2x interpolation, DATACLK output mode, dual-port
mode, 50
double-terminated outputs, external reference at 1.25V, TA = -40°C to +85°C, unless otherwise noted. Typical values are
at TA = +25°C, unless otherwise noted.) (Note 2)
Note 2: All limit specifications are 100% tested at TA ≥ +25°C. Specifications at TA < +25°C are guaranteed by design and characterization.
Note 3: 3.84MHz bandwidth, single carrier.
Note 4: Excludes data latency.
Note 5: Measured single-ended into a 50
load.
Note 6: Excludes sin(x)/x rolloff.
Note 7: Guaranteed by design and characterization.
Note 8: Setup and hold time specifications characterized with 3.3V CMOS logic levels.
Note 9: Parameter defined as the change in midscale output caused by a ±5% variation in the nominal supply voltage.
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