cies of fIM
參數(shù)資料
型號: MAX5893EGK+D
廠商: Maxim Integrated Products
文件頁數(shù): 17/32頁
文件大?。?/td> 0K
描述: IC DAC 12BIT DUAL 500MSPS 68-QFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 30
設(shè)置時間: 11ns
位數(shù): 12
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 模擬和數(shù)字
功率耗散(最大): 511mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 68-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 68-QFN 裸露焊盤(10x10)
包裝: 管件
輸出數(shù)目和類型: 2 電流,單極
采樣率(每秒): 500M
MAX5893
Digital Modulator
The MAX5893 features digital modulation at frequen-
cies of fIM/2 and fIM/4, where fIM is the data rate at the
input to the modulator. fIM equals fDAC in 1x, 2x, and 4x
interpolation modes. In 8x interpolation mode, fIM
equals fDAC/2. The output rate of the modulator is
always the same as the input data rate to the modula-
tor, fIM.
In complex modulation mode, data from the second
interpolation filter is frequency mixed with the on-chip
in-phase and quadrature (I/Q) local oscillator (LO).
Complex modulation provides the benefit of image
sideband rejection when combined with an external
quadrature modulator commonly found in wireless
communication systems.
In the fLO = fIM/4 mode, real or complex modulation can
be used. The modulator multiplies successive input data
samples by the sequence [1, 0, -1, 0] for a cos(
ωt). The
modulator modulates the input signal up to fIM/4, creat-
ing upper and lower images around fIM/4. The quadra-
ture LO sin(
ωt) is realized by delaying the cos(ωt)
sequence by one clock cycle. Using complex modula-
tion, complex IF is generated. The complex IF combined
with an external quadrature modulator provides image
rejection. The sign of the LO can be changed to allow
the user to select whether the upper or the lower image
should be rejected (bit 1 of register 01h).
When fIM/2 is chosen as the LO frequency, the input
signal is multiplied by [-1, 1] on both channels. This pro-
duces images around fIM/2. The complex image-reject
modulation mode is not available for this LO frequency.
The outputs of the modulator can be expressed as:
in complex modulation, e+jwt
in complex modulation, e-jwt
where
ω = 2 x π x fLO.
For real modulation, the outputs of the modulator can
be expressed as:
If more than one MAX5893 is used, their LO phases
can be synchronized by simultaneously releasing
RESET. This sets the MAX5893 to its predefined initial
phase.
Device Reset
The MAX5893 can be reset by holding the RESET pin
low for 10ns. This will program the control registers to
their default values in Table 2. During power-on, RESET
must be held low until all power supplies have stabi-
lized. Alternatively, programming bit 5 of address 00h
to a logic-high also resets the MAX5893 after power-up.
It
A t
t
Qt
A t
t
()= () × ()
cos
ω
It
A t
t
B t
t
Qt
A t
t
B t
t
()= () × ()+ () × ()
cos
sin
cos
ωω
It
A t
t
B t
t
Qt
A t
t
B t
t
()= () × () ( ) × ()
()= () × ()+ () × ()
cos
sin
cos
ωω
12-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
24
______________________________________________________________________________________
Figure 13. (a) Modulator in Complex Modulation Mode; (b) Modulator in Real Modulation Mode
sin(
ωt)
sin(
ωt)
cos(
ωt)
cos(
ωt)
I-CHANNEL
INPUT DATA
TO
FIR3
(a)
Q-CHANNEL
INPUT DATA
I-CHANNEL
OUTPUT DATA
Q-CHANNEL
OUTPUT DATA
(b)
sin(
ωt)
sin(
ωt)
cos(
ωt)
cos(
ωt)
I-CHANNEL
INPUT DATA
TO
FIR3
Q-CHANNEL
INPUT DATA
I-CHANNEL
OUTPUT DATA
Q-CHANNEL
OUTPUT DATA
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