參數(shù)資料
型號(hào): MAX5891EGK+D
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 2/16頁(yè)
文件大小: 0K
描述: IC DAC 16BIT LVDS 600MSPS 68-QFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 30
設(shè)置時(shí)間: 11ns
位數(shù): 16
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 模擬和數(shù)字
功率耗散(最大): 301mW
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 68-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 68-QFN 裸露焊盤(pán)(10x10)
包裝: 管件
輸出數(shù)目和類(lèi)型: 2 電流,單極
采樣率(每秒): 600M
產(chǎn)品目錄頁(yè)面: 1398 (CN2011-ZH PDF)
MAX5891
Clock Inputs (CLKP, CLKN)
To achieve the best possible jitter performance, the
MAX5891 features flexible differential clock inputs
(CLKP, CLKN) that operate from a separate clock
power supply (AVCLK). Drive the differential clock
inputs from a single-ended or a differential clock
source. For highest dynamic performance, differential
clock source is required. For single-ended operation,
drive CLKP and bypass CLKN to CGND.
CLKP and CLKN are internally biased at AVCLK / 2,
allowing the AC-coupling of clock sources directly to
the device without external resistors to define the DC
level. The input resistance from CLKP and CLKN to
ground is approximately 5k
Ω.
Data-Timing Relationship
Figure 3 shows the timing relationship between digital
LVDS data, clock, and output signals. The MAX5891
features a 2.6ns hold, a -1.5ns setup, and a 2.5ns prop-
agation delay time. There is a 5.5 clock-cycle latency
between data write operation and the corresponding
analog output transition.
LVDS Data Inputs
The MAX5891 has 16 pairs of LVDS data inputs (offset
binary format) and can accept data rates up to
600Mwps. Each differential input pair is terminated with
an internal 110
Ω resistor. The common-mode input
resistance is 3.2k
Ω.
Power-Down Operation (PD)
The MAX5891 features a power-down mode that
reduces the DAC’s power consumption. Set PD high to
power down the MAX5891. Set PD low or leave uncon-
nected for normal operation.
When powered down, the MAX5891 overall power con-
sumption is reduced to less than 13W. The MAX5891
requires 350s to wake up from power-down and enter
a fully operational state if the external reference is
used. If the internal reference is used, the power-down
recovery time is 10ms. The PD internal pulldown circuit
sets the MAX5891 in normal mode when PD is left
unconnected.
16-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
10
______________________________________________________________________________________
IOUT
OUTN OUTP
CURRENT
SOURCES
CURRENT
SWITCHES
AVDD3.3
Figure 2. Simplified Analog Output Structure
D0–D16
tSETUP
tHOLD
DN
CLKP
CLKN
DN + 2
DN + 4
DN + 6
IOUTP
IOUTN
tPD
DN + 1
DN + 3
DN + 5
DN + 7
OUTN - 2
OUTN - 3
OUTN - 4
OUTN - 5
OUTN - 6
OUTN - 7
OUTN-1
OUTN
Figure 3. Timing Relationship Between Clock, Input Data, and Analog Output
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