參數(shù)資料
型號： MAX5890EGK+D
廠商： Maxim Integrated Products
文件頁數(shù)： 12/16頁
文件大?。?/td> 0K
描述： IC DAC 14BIT LVDS 600MSPS 68-QFN
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 30
設(shè)置時間： 11ns
位數(shù)： 14
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 298mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 68-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 68-QFN 裸露焊盤（10x10）
包裝： 管件
輸出數(shù)目和類型： 2 電流，單極
采樣率（每秒）： 600M
MAX5890
14-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
_______________________________________________________________________________________
5
Note 2: This parameter does not include update-rate-dependent effects of sin(x)/x filtering inherent in the MAX5890.
Note 3: Parameter measured single-ended with 50
double-terminated outputs.
Note 4: Not production tested. Guaranteed by design.
Note 5: Parameter defined as the change in midscale output caused by a
±5% variation in the nominal supply voltages.
Note 6: Not production tested. Guaranteed by design.
Note 7: Differential input voltage defined as VD_P - VD_N.
Note 8: Combination of logic-high/-low and common-mode voltages must not exceed absolute maximum rating for D_P/D_N inputs.
ELECTRICAL CHARACTERISTICS (continued)
(AVDD3.3 = DVDD3.3 = AVCLK = 3.3V, AVDD1.8 = DVDD1.8 = 1.8V, external reference VREFIO = 1.2V, output load 50
double-terminat-
ed, transformer-coupled output, IOUT = 20mA, TA = -40°C to +85°C, unless otherwise noted. Specifications at TA
≥ +25°C are guar-
anteed by production testing. Specifications at TA < +25°C are guaranteed by design and characterization. Typical values are at TA
= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input Resistance
RCLK
Single-ended
5
k
Input Capacitance
CCLK
3pF
POWER SUPPLIES
AVDD3.3
3.135
3.3
3.465
Analog Supply Voltage Range
AVDD1.8
1.710
1.8
1.890
V
Clock Supply Voltage Range
AVCLK
3.135
3.3
3.465
V
DVDD3.3
3.135
3.3
3.465
Digital Supply Voltage Range
DVDD1.8
1.710
1.8
1.890
V
fCLK = 100MHz, fOUT = 16MHz
26.5
fCLK = 500MHz, fOUT = 16MHz
26.5
28.5
IAVDD3.3
fCLK = 600MHz, fOUT = 16MHz
26.5
fCLK = 100MHz, fOUT = 16MHz
11.3
fCLK = 500MHz, fOUT = 16MHz
50
58
Analog Supply Current
IAVDD1.8
fCLK = 600MHz, fOUT = 16MHz
60
mA
fCLK = 100MHz, fOUT = 16MHz
2.8
fCLK = 500MHz, fOUT = 16MHz
2.8
3.6
Clock Supply Current
IAVCLK
fCLK = 600MHz, fOUT = 16MHz
2.8
mA
fCLK = 100MHz, fOUT = 16MHz
0.2
fCLK = 500MHz, fOUT = 16MHz
0.2
0.5
IDVDD3.3
fCLK = 600MHz, fOUT = 16MHz
0.2
fCLK = 100MHz, fOUT = 16MHz
10.6
fCLK = 500MHz, fOUT = 16MHz
43
49
Digital Supply Current
IDVDD1.8
fCLK = 600MHz, fOUT = 16MHz
50.5
mA
fCLK = 100MHz, fOUT = 16MHz
137
fCLK = 500MHz, fOUT = 16MHz
264
298
fCLK = 600MHz, fOUT = 16MHz
297
mW
Total Power Dissipation
PDISS
Power-down, clock static low,
data input static
13
W
Power-Supply Rejection Ratio
PSRR
(Note 5)
±0.025
%FS
VD_N
VD_P
VIHLVDS
VILLVDS
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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