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參數(shù)資料
| 型號： | MAX5888EVKIT |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Evaluation Kit for the MAX5886/MAX5887/MAX5888 |
| 中文描述： | MAX5886、MAX5887、MAX5888評估板 |
| 文件頁數(shù)： | 2/14頁 |
| 文件大小： | 382K |
| 代理商： | MAX5888EVKIT |
E
MAX5858A Evaluation Kit
2
_______________________________________________________________________________________
Component Suppliers
SUPPLIER
PHONE
847-639-6400
714-373-7366
847-803-6100
972-644-5580
FAX
WEBSITE
Coilcraft
Panasonic
TDK
Texas Instruments
847-639-1469
714-737-7323
847-390-4405
214-480-7800
www.coilcraft.com
www.panasonic.com
www.component.tdk.com
www.ti.com
Note:
Please indicate that you are using the MAX5858A when contacting these component suppliers.
Quick Start (PLL Disabled)
Note:
To evaluate PLL-enabled mode, see the
Quick
Start (PLL Enabled)
section.
Recommended Equipment
DC power supplies:
Digital 3V, 500mA
Analog 3V, 100mA
Clock 3V, 200mA
Two RF signal generators with low phase noise and
low jitter for the clock input (e.g., HP 8662A)
Data generator (e.g., Sony/Tektronix DG2020A)
Two variable output PODs (e.g., Sony/Tektronix
P3420)
Spectrum analyzer
Oscilloscope
Digital voltmeter
The MAX5858A EV kit is a fully assembled and tested
surface-mount board. Follow the steps below for board
operation.
Do not turn on power supplies or enable
signal generators until all connections are completed
(Figure 1):
1) Verify that no shunt is installed across jumper JU1
(the CLKIN SMA connector on the EV kit is not used
for evaluating the MAX5858A in PLL disabled
mode).
2) Verify that a shunt is installed across jumper JU2
(no DC offset at single-ended analog outputs OUTA
and OUTB).
3) Verify that a shunt is installed across jumper JU3
(IDE disabled).
4) Verify that a shunt is installed across jumper JU4
(PLL disabled).
5) Verify that a shunt is installed across jumper JU5
(
REN
enabled, internal reference enabled).
6) Verify that shunts are installed across jumpers
JU6–JU9 (differential output mode).
7) Verify that no shunts are installed across jumpers
JU10 and JU11. (CLKXP and CLKXN are used for
evaluating the MAX5858A in PLL disabled mode).
8) Connect the RF OUTPUT of the master HP 8662A
(data clock) to the clock input on the back side of
the data generator (Sony/Tektronix DG2020A). (See
Figure 1 for the equipment setup connections.)
Component List (continued)
DESIGNATION
QTY
DESCRIPTION
T1, T3, T5, T6
4
Transformers
Coilcraft Z9370-B
T2, T4
2
Transformers
Coilcraft Z9301-B
U1
1
MAX5858AECM (48-pin TQFP–EP)
DESIGNATION
QTY
DESCRIPTION
U2
1
Quadruple bus buffer gate with
tri-state outputs ( 14- p n TS S O P P W)
Texas Instruments
SN74ALVC125PWR
None
11
Shunts (JU1, JU10, JU11 any one
pin), (JU2–JU9 pins 1-2)
None
1
MAX5858A PC board
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