參數(shù)資料
型號： MAX5886EGK+TD
廠商： Maxim Integrated Products
文件頁數(shù)： 12/18頁
文件大?。?/td> 0K
描述： IC DAC 12BIT 3.3V 500MSPS 68-QFN
產(chǎn)品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 2,500
設置時間： 11ns
位數(shù)： 12
數(shù)據(jù)接口： 并聯(lián)
轉換器數(shù)目： 1
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 130mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 68-VFQFN 裸露焊盤
供應商設備封裝： 68-QFN 裸露焊盤（10x10）
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 2 電流，單極
采樣率（每秒）： 500M
MAX5886
3.3V, 12-Bit, 500Msps High Dynamic
Performance DAC with Differential LVDS Inputs
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = VCLK = 3.3V, AGND = DGND = CLKGND = 0, external reference, VREFIO = 1.25V, differential transformer-coupled
analog output, 50
double terminated (Figure 7), IOUT = 20mA, TA = TMIN to TMAX, unless otherwise noted. ≥+25°C guaranteed by
production test, <+25°C guaranteed by design and characterization. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
fOUT = 10MHz, -12dB FS
81
fCLK = 100MHz
fOUT = 30MHz, -12dB FS
76
fOUT = 10MHz, -12dB FS
71
fOUT = 16MHz, -12dB FS,
TA
≥ +25°C
69
76
fOUT = 50MHz, -12dB FS
72
fCLK = 200MHz
fOUT = 80MHz, -12dB FS
64
fOUT = 10MHz, -12dB FS
66
fOUT = 30MHz, -12dB FS
63
fOUT = 50MHz, -12dB FS
65
Spurious-Free Dynamic Range to
Nyquist
SFDR
fCLK = 500MHz
fOUT = 80MHz, -12dB FS
58
dBc
fCLK = 200MHz
fOUT1 = 9MHz, -6dB FS,
fOUT2 = 10MHz, -6dB FS
-85
2-Tone IMD
TTIMD
fCLK = 200MHz
fOUT1 = 79MHz, -6dB FS,
fOUT2 = 80MHz, -6dB FS
-61
dBc
4-Tone IMD, 1MHz Frequency
Spacing, GSM Model
FTIMD
fCLK = 300MHz
fOUT = 32MHz, -12dB FS
-78
dBc
Adjacent Channel Leakage
Power Ratio, 4.1MHz Bandwidth,
WCDMA Model
ACLR
fCLK =
184.32MHz
fOUT = 61.44MHz
70
dB
Output Bandwidth
BW-1dB
(Note 2)
450
MHz
REFERENCE
Internal Reference Voltage Range
VREFIO
1.12
1.22
1.32
V
Reference Voltage Drift
TCOREF
±50
ppm/
°C
Reference Input Compliance
Range
VREFIOCR
0.1
1.25
V
Reference Input Resistance
RREFIO
10
k
ANALOG OUTPUT TIMING
Output Fall Time
tFALL
90% to 10% (Note 3)
375
ps
Output Rise Time
tRISE
10% to 90% (Note 3)
375
ps
Output Voltage Settling Time
tSETTLE
Output settles to 0.025% FS (Note 3)
11
ns
Output Propagation Delay
tPD
(Note 3)
1.8
ns
Glitch Energy
1
pV-s
IOUT = 2mA
30
Output Noise
NOUT
IOUT = 20mA
30
pA/
√Hz
TIMING CHARACTERISTICS
Data to Clock Setup Time
tSETUP
Referenced to rising edge of clock (Note 4)
-0.8
ns
Data to Clock Hold Time
tHOLD
Referenced to rising edge of clock (Note 4)
1.8
ns
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參數(shù)描述
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