參數(shù)資料
型號: MAX5886EGK+D
廠商: Maxim Integrated Products
文件頁數(shù): 7/18頁
文件大?。?/td> 0K
描述: IC DAC 12BIT 3.3V 500MSPS 68-QFN
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 30
設(shè)置時間: 11ns
位數(shù): 12
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 模擬和數(shù)字
功率耗散(最大): 130mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 68-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 68-QFN 裸露焊盤(10x10)
包裝: 管件
輸出數(shù)目和類型: 2 電流,單極
采樣率(每秒): 500M
產(chǎn)品目錄頁面: 1398 (CN2011-ZH PDF)
MAX5886
3.3V, 12-Bit, 500Msps High Dynamic
Performance DAC with Differential LVDS Inputs
______________________________________________________________________________________
15
supply decoupling guidelines for high-speed, high-fre-
quency applications should be closely followed.
This reduces EMI and internal crosstalk that can signifi-
cantly affect the dynamic performance of the MAX5886.
Use of a multilayer printed circuit (PC) board with sepa-
rate ground and power-supply planes is recommend-
ed. High-speed signals should run on lines directly
above the ground plane. Since the MAX5886 has sepa-
rate analog and digital ground buses (AGND,
CLKGND, and DGND, respectively), the PC board
should also have separate analog and digital ground
sections with only one point connecting the two planes.
Digital signals should be run above the digital ground
plane and analog/clock signals above the analog/clock
ground plane. Digital signals should be kept as far
away from sensitive analog inputs, reference input
sense lines, common-mode input, and clock inputs as
practical. A symmetric design of clock input and ana-
log output lines is recommended to minimize 2nd-order
harmonic distortion components and optimize the
DAC’s dynamic performance. Digital signal paths
should be kept short and run lengths matched to avoid
propagation delay and data skew mismatches.
The MAX5886 supports three separate power-supply
inputs for analog (AVDD), digital (DVDD), and clock
(VCLK) circuitry. Each AVDD, DVDD, and VCLK input
should at least be decoupled with a separate 0.1F
capacitor as close to the pin as possible and their
opposite ends with the shortest possible connection to
the corresponding ground plane (Figure 13). Try to
minimize the analog and digital load capacitances for
optimized operation. All three power-supply voltages
should also be decoupled at the point they enter the
PC board with tantalum or electrolytic capacitors.
Ferrite beads with additional decoupling capacitors
forming a pi network could also improve performance.
The analog and digital power-supply inputs AVDD,
VCLK, and DVDD of the MAX5886 allow a supply volt-
age range of 3.3V ±5%.
The MAX5886 is packaged in a 68-pin QFN-EP
(package code: G6800-4), providing greater design
flexibility, increased thermal efficiency**, and optimized
AC performance of the DAC. The exposed pad (EP)
enables the user to implement grounding techniques,
which are necessary to ensure highest performance
operation. The EP must be soldered down to AGND.
O
-30
-60
-70
-73
-75
-80
-90
0.2
0.4 0.6
1.2
1.8
6.0
IMD REQUIREMENT: < -70dBc
30kHz 100kHz
MEASUREMENT BANDWIDTH
TRANSMITTER
EDGE
INBAND
OUTBAND
WORST-CASE
NOISE LEVEL
AMPLITUDE
(dBc)
FREQUENCY OFFSET FROM CARRIER (MHz)
Figure 11. GSM/EDGE Tx Mask Requirements
-100
-70
-80
-90
-60
-50
-40
-30
-20
-10
0
26
30
28
34
32
36
38
4-TONE MULTITONE POWER RATIO PLOT
(fCLK = 300MHz, fCENTER = 31.604MHz)
fOUT (MHz)
OUTPUT
POWER
(dBm)
fT2
fT3
fT4
fT1
AOUT = -12dB FS
BW = 12MHz
fT1 = 29.6997MHz
fT2 = 30.7251MHz
fT3 = 32.4829MHz
fT4 = 34.0209MHz
Figure 12. 4-Tone MTPR Test Results
**Thermal efficiency is not the key factor, since the MAX5886 features low-power operation. The exposed pad is the key element to
ensure a solid ground connection between the DAC and the PC board’s analog ground layer.
相關(guān)PDF資料
PDF描述
MAX5887EGK+D IC DAC 14BIT 3.3V 500MSPS 68-QFN
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