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參數(shù)資料
| 型號： | MAX5885EGM+D |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 2/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 16BIT 3.3V 200MSPS 48-QFN |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 43 |
| 設置時間： | 11ns |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 135mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-QFN 裸露焊盤 |
| 供應商設備封裝： | 48-QFN-EP（7x7） |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 2 電流，單極 |
| 采樣率（每秒）： | 200M |
| 產(chǎn)品目錄頁面： | 1398 (CN2011-ZH PDF) |
MAX5885
3.3V, 16-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
10
______________________________________________________________________________________
Although not recommended because of additional
noise pickup from the ground plane, for single-ended
operation IOUTP should be selected as the output, with
IOUTN connected to AGND. Note that a single-ended
output configuration has a higher 2nd-order harmonic
distortion at high output frequencies than a differential
output configuration.
Figure 3 displays a simplified diagram of the
MAX5885’s internal output structure.
Clock Inputs (CLKP, CLKN)
The MAX5885 features a flexible differential clock input
(CLKP, CLKN) operating from separate supplies
(VCLK, CLKGND) to achieve the best possible jitter
performance. The two clock inputs can be driven from
a single-ended or a differential clock source. For sin-
gle-ended operation, CLKP should be driven by a logic
source, while CLKN should be bypassed to AGND with
a 0.1F capacitor.
The CLKP and CLKN pins are internally biased to VCLK/2.
This allows the user to AC-couple clock sources directly
to the device without external resistors to define the DC
level. The input resistance of CLKP and CLKN is >5k
.
See Figure 4 for a convenient and quick way to apply a
differential signal created from a single-ended source
(e.g., HP 8662A signal generator) and a wideband
transformer. These inputs can also be driven from a
CMOS-compatible clock source; however, it is recom-
mended to use sinewave or AC-coupled ECL drive for
best performance.
Data Timing Relationship
Figure 5 shows the timing relationship between differ-
ential, digital CMOS data, clock, and output signals.
The MAX5885 features a 1.25ns hold, a 0.4ns setup,
and a 1.8ns propagation delay time. There is a 3.5
clock-cycle latency between CLKP/CLKN transitioning
high/low and IOUTP/IOUTN.
CMOS-Compatible Digital Inputs (B0–B15)
The MAX5885 features single-ended, CMOS-compatible
receivers on the bus input interface. These CMOS inputs
(B0–B15) allow for a voltage swing of 3.3V.
Segment Shuffling (SEL0)
Segment shuffling can improve the SFDR of the
MAX5885 at higher output frequencies and amplitudes.
Note that an improvement in SFDR can only be achieved
at the cost of a slight increase in the DAC’s noise floor.
Pin SEL0 controls the segment-shuffling function. If SEL0
is pulled low, the segment-shuffling function of the DAC is
disabled. SEL0 can also be left open, because an internal
pulldown resistor helps to deactivate the segment-shuf-
fling feature. To activate the MAX5885 segment-shuffling
function, SEL0 must be pulled high.
XOR Function (XOR)
The MAX5885 is equipped with a single-ended, CMOS-
compatible XOR input, which may be left open (XOR
provides an internal pulldown resistor) or pulled down
to DGND, if not used. Input data is XORed with the bit
applied to the XOR pin. Pulling XOR high inverts the
input data. Pulling XOR low leaves the input data nonin-
verted. By applying a pseudorandom bit stream to XOR
and applying data while XOR is high, the bit transitions
in the digital input data can be decorrelated from the
DAC output, allowing the user to troubleshoot possible
spurious or harmonic distortion degradation due to dig-
ital feedthrough on the PC board.
SINGLE-ENDED
CLOCK SOURCE
(e.g., HP 8662A)
1:1
WIDEBAND RF TRANSFORMER
PERFORMS SINGLE-ENDED TO
DIFFERENTIAL CONVERSION.
TO
DAC
CLKP
0.1
F
0.1
F
CLKN
CLKGND
25
25
Figure 4. Differential Clock Signal Generation
IOUT
IOUTN
IOUTP
CURRENT
SOURCES
CURRENT
SWITCHES
AVDD
Figure 3. Simplified Analog Output Structure
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MAX5885EGM-T | 制造商:Maxim Integrated Products 功能描述:3.3V, 16-BIT, 200MSPS HIGH DYNAMIC PERFORMAN - Tape and Reel |
| MAX5885EGM-TD | 功能描述:數(shù)模轉換器- DAC RoHS:否 制造商:Texas Instruments 轉換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| MAX5885EVKIT | 功能描述:數(shù)模轉換器- DAC Evaluation Kit for the MAX5883 MAX5884 MAX5885 RoHS:否 制造商:Texas Instruments 轉換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| MAX5886EGK | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: |
| MAX5886EGK+D | 功能描述:數(shù)模轉換器- DAC 12-Bit 500Msps DAC RoHS:否 制造商:Texas Instruments 轉換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
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