參數(shù)資料
型號: MAX5874EGK+D
廠商: Maxim Integrated Products
文件頁數(shù): 16/16頁
文件大?。?/td> 0K
描述: IC DAC 14BIT 200MSPS DUAL 68-QFN
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 30
設置時間: 14ns
位數(shù): 14
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 模擬和數(shù)字
功率耗散(最大): 300mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 68-VFQFN 裸露焊盤
供應商設備封裝: 68-QFN 裸露焊盤(10x10)
包裝: 管件
輸出數(shù)目和類型: 4 電流,單極
采樣率(每秒): 200M
產(chǎn)品目錄頁面: 1398 (CN2011-ZH PDF)
MAX5874
14-Bit, 200Msps, High-Dynamic-Performance,
Dual DAC with CMOS Inputs
_______________________________________________________________________________________
9
Detailed Description
Architecture
The MAX5874 high-performance, 14-bit, dual current-
steering DAC (Figure 1) operates with DAC update rates
up to 200Msps. The converter consists of input registers
and a demultiplexer for single-port (interleaved) mode,
followed by a current-steering array. During operation in
interleaved mode, the input data registers demultiplex
the single-port data bus. The current-steering array gen-
erates differential full-scale currents in the 2mA to 20mA
range. An internal current-switching network, in combina-
tion with external 50 termination resistors, converts the
differential output currents into dual differential output
voltages with a 0.1V to 1V peak-to-peak output voltage
range. An integrated 1.2V bandgap reference, control
amplifier, and user-selectable external resistor determine
the data converter’s full-scale output range.
Reference Architecture and Operation
The MAX5874 supports operation with the internal 1.2V
bandgap reference or an external reference voltage
source. REFIO serves as the input for an external, low-
impedance reference source. REFIO also serves as a
reference output when the DAC operates in internal ref-
erence mode. For stable operation with the internal ref-
erence, decouple REFIO to GND with a 1F capacitor.
Due to its limited output-drive capability, buffer REFIO
with an external amplifier when driving large
external loads.
The MAX5874’s reference circuit (Figure 2) employs a
control amplifier to regulate the full-scale current
IOUTFS for the differential current outputs of the DAC.
Calculate the full-scale output current as follows:
where IOUTFS is the full-scale output current of the
DAC. RSET (located between FSADJ and DACREF)
determines the amplifier’s full-scale output current for
the DAC. See Table 1 for a matrix of different IOUTFS
and RSET selections.
I
V
R
OUTFS
REFIO
SET
×
32
1
2
14
Pin Description (continued)
PIN
NAME
FUNCTION
42
XOR
DAC Exclusive-OR Select Input. Set XOR low to allow the data stream to pass unchanged to the
DAC input. Set XOR high to invert the input data into the DAC. If unused, connect XOR to GND.
44
SELIQ
DAC Select Input. Set SELIQ low to direct data into the Q-DAC inputs. Set SELIQ high to direct
data into the I-DAC inputs. If unused, connect SELIQ to GND. SELIQ’s logic state is only valid in
single-port (interleaved) mode.
45–58
B13, B12, B11,
B10, B9, B8,
B7, B6, B5, B4,
B3, B2, B1, B0
Data Bits B13–B0. In dual-port mode, data is directed to the I-DAC. In single-port mode, the state
of SELIQ determines where the data bits are directed.
61
DVDD1.8
Digital Supply Voltage. Accepts a 1.71V to 1.89V supply voltage range. Bypass with a 0.1F
capacitor to GND.
62–68
A13, A12, A11,
A10, A9, A8, A7
Data Bits A13–A7. In dual-port mode, data is directed to the Q-DAC. In single-port mode, data
bits are not used. Connect bits A13–A7 to GND in single-port mode.
EP
Exposed Pad. Must be connected to GND through a low-impedance path.
Table 1. IOUTFS and RSET Selection
Matrix Based on a Typical 1.200V
Reference Voltage
RSET (
)
FULL-SCALE
CURRENT IOUTFS (mA)
CALCULATED
1% EIA STD
2
19.2k
19.1k
5
7.68k
7.5k
10
3.84k
3.83k
15
2.56k
2.55k
20
1.92k
1.91k
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